Design won't fit in device

[Altera_Forum]

Hi, 

 I'm trying to get a design to fit in a Stratix III EP3SL340H1152CS device. I get an error saying that the fitter requires 13555 LABs to implement but device only contains 13520 LABs.   I was told that they way the software works is that if the device is more than, say, ~85% full, then the fitter will fail even though it could actually place and route it. There's some sort of threshold where the fitter would just stop. Is there something like this in operation?   Thanks   MT

[Altera_Forum]

hi, 

the problem may be a memory problem, if you used a lot of memory space. good luck

[Altera_Forum]

Thanks for the reply. 

 I think the design started out not using memory but then memory was used to cut down the size of some very large fifo's. I was curious about the how the fitter may see things i.e. if it doesn't see, say, 20% of the device empty, it won't attempt to fit.

[Altera_Forum]

OK, sometimes the design occupies 20% and place and route fail, because there are resources such as memory cells or DSP are used by design!  then tchek that the report gives the fitter to see the resources are fully utilized. good luck 

[Altera_Forum]

Hi, 

 Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).    The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.   Kaz

[Altera_Forum]

--- Quote Start ---  Hi,   Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).    The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.   Kaz  --- Quote End ---     What settings are using ? E.g. optimize for speed or physical synthesis ....

[Altera_Forum]

Some settings: 

 1. physical_synthesis_map_logic_to_memory_for_area = on   2. physical_synthesis_combo_logic_for_area = on   3. fmax is set to 125MHz   4. mux_restructure = on   5. allow_any_ram_size_for_recognition = on   6. allow_any_rom_size_for_recognition = on   7. allow_any_shift_register_size_for_recognition = on   8. auto_packed_registers_stratixii = minimise area   9. fitter_effort = standard fit   10. router_effort_multuplier = 2.0   11. router_timing_optimization_level = maximum   12. partition_fitter_preservation_level = placement and routing   13. smart_recompile = on   15. stratixii_optimisation_technique = area   It takes several hours just to get to the fitter stage.   Regards   MT

[Altera_Forum]

--- Quote Start ---  Some settings:   1. physical_synthesis_map_logic_to_memory_for_area = on   2. physical_synthesis_combo_logic_for_area = on   3. fmax is set to 125MHz   4. mux_restructure = on   5. allow_any_ram_size_for_recognition = on   6. allow_any_rom_size_for_recognition = on   7. allow_any_shift_register_size_for_recognition = on   8. auto_packed_registers_stratixii = minimise area   9. fitter_effort = standard fit   10. router_effort_multuplier = 2.0   11. router_timing_optimization_level = maximum   12. partition_fitter_preservation_level = placement and routing   13. smart_recompile = on   15. stratixii_optimisation_technique = area   It takes several hours just to get to the fitter stage.   Regards   MT  --- Quote End ---     Hi,  are you using design partitions in your Quartus project ? If, yes try a run where you remove all design partitions. Another reason could be memory description which are not recognized or could not implemented in the memory of the FPGA. So have look to the to the compilation report : Analysis & Synthesis -> Resource Uitlization by Entity  Are memory and DSP blocks (e.g.) used etc......

[Altera_Forum]

Thanks for the info. 

 From what I can see in the report, block memory is being used. However, no DSP blocks are being used.   I don't know much about the design at this stage as I've added some logic to it at a very low level, so, I'm finding my way round it too. I don't know what this 'partition_fitter_preservation_level' refers to. I would like to try it completely flattened with no incremental synthesis or anything like that. Right now, I just want it to fit.

[Altera_Forum]

Fitter Preservation Level: Allows you to specify the amount of information that you want the Fitter to preserve from the specified netlist file. Fitter Preservation Level is only available when Full incremental compilation is turned on.

[Altera_Forum]

--- Quote Start ---  Fitter Preservation Level: Allows you to specify the amount of information that you want the Fitter to preserve from the specified netlist file. Fitter Preservation Level is only available when Full incremental compilation is turned on.  --- Quote End ---    Does the design fit into the FPGA before you changed it ?

[Altera_Forum]

Yes, it did. I've disabled most of the logic that I added and kept it to it's minimum. I've tried many combinations of options and the best ones (as usual the original ones) puts the design 18 labs too big. 

 Does Quartus do multiple attempts if it fails to fit? Is there a way of finding out quickly that it's likely to fail?

[Altera_Forum]

If the report suggests that there are enough LEs but too few LABs then it's probably a routing problem rather than a logic problem. Enabling the automatic insertion of logic and registers can help this. 

 Tools>>Advisors>> Resource Optimisation Advisor might help - there's a section there on routing resource.

[Altera_Forum]

--- Quote Start ---  Yes, it did. I've disabled most of the logic that I added and kept it to it's minimum. I've tried many combinations of options and the best ones (as usual the original ones) puts the design 18 labs too big.  Does Quartus do multiple attempts if it fails to fit? Is there a way of finding out quickly that it's likely to fail?  --- Quote End ---      The fitter tries a maximum of 3 placement and routing attempts, with each successive attempt increasing the placement effort and hence increasing compilation times. You can limit it to one attempt.  Settings -> Fitter Settings -> Limit to one fitting attempt  When the design fits, what was the device utilization, the peak and the average routing usage ?   What kind of design is it ? Digital signal processing ????

[Altera_Forum]

We've solved this one now. Not all the FIFO's we're using block ram - some use registers because it's move efficient. Altering that ratio - putting more in block memory solved the problem.

[Altera_Forum]

--- Quote Start ---  I get an error saying that the fitter requires 13555 LABs to implement but device only contains 13520 LABs.  --- Quote End ---      --- Quote Start ---  If the report suggests that there are enough LEs but too few LABs then it's probably a routing problem rather than a logic problem.  --- Quote End ---     I think I've never known of this kind of no-fit error being related to routing other than at the LAB control signal level. The device handbook documents how many clocks, clock enables, asynchronous clears, etc. are available in each LAB. For example, a device might support only two clock enables in a LAB. If the Fitter has placed two registers in the LAB using two different clock enables, then the Fitter can't place any registers in that LAB using any other clock enable. When the "Control Signals" table in the Fitter report lists a huge number of one of these categories of signals (typically it will be clock enables), this device restriction can make it difficult or impossible for the Fitter to group registers into few enough LABs to fit. This can happen even when the logic utilization is well below 100%.

[Altera_Forum]

--- Quote Start ---  We've solved this one now. Not all the FIFO's we're using block ram - some use registers because it's move efficient. Altering that ratio - putting more in block memory solved the problem.  --- Quote End ---    Great, when you look to the resources for the entities did you see an unusual ratio between the number of LCELL and Registers for the block where the Fifos are in ?

[Altera_Forum]

The design uses a lot fo FIFO's and you could see the difference in the number of lcells and registers being used in the ones without the block ram and that ones with. I'm sure if all the fifo's used block ram then there would probably be problems again.

[Altera_Forum]

--- Quote Start ---  Hi,   Your resource problem is the logic, not memory blocks as indicated by the error message(LABs).    The notion of 85% or so is sort of rule of thumb for fmax. The fitter doesn't follow this rule. It will fit as long as there is resource until 100% if necessary.   Kaz  --- Quote End ---     Hi   I do have a problem with compilation when setting the on-chip RAM to 60kb on a Cyclone 3c25. I once did that and the project compiled without any problem. But now it wont work even in a simple project. I only intend to use on-chip memory to use 'fopen' and 'fclose' in my C code. I dont know what could be the problem if it did work once. Please help.