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RFrac
Beginner
1,029 Views

Arria 10 EMIF PLL reference clock I/O standard for DDR3L

I have some doubts about connecting clock source to hard memory controller in Arria 10 GX. I can’t find this in EMIF and other chip documentation.

 

1. I’m connecting DDR3L memory with 1,35 V power supply. On Arria 10 GX memory banks are supplied with 1,35 V. In Quartus 18 project there’s altera_emif module, witch has these settings on FPGA I/O tab:

- protocol: DDR3

- voltage: 1.35 V (DDR3L)

- PLL reference clock I/O standard: LVDS with On-Chip Termination.

 

Clock source has LVDS output and it’s connected to dedicated clock input in hard memory controller. Whole project compiles without errors, however I’m wondering:

- usually LVDS on Altera devices requires 1,8 V bank voltage to achieve common mode voltage Vcm=1,25 V. Here I have receiver in 1,35 V bank – is this still compatible with LVDS?

 

2. My clock source cannot achieve Vcm=1,25 V, it has Vcm =0,9 V and 400 mVpp swing. Is it compatible with PLL refclk input on hard memory controller with LVDS input and 1,35 V bank supply?

 

3. I cannot find any information about internal bias of pll refclk input on hard memory controller in Arria 10 GX. I’m using DC connection between clock and FPGA and I like to use on chip termination. Does “LVDS with On-Chip Termination” for PLL refclk input mean that there’s 100 Ohm parallel termination and no bias? When I tried simulation with IBIS model generated from Quartus this input had internal bias (when separated on AC link), however most documentation on LVDS in Intel FPGAs states, that LVDS I/O’s have no internal bias.

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4 Replies
NurAida_A_Intel
Employee
27 Views

Hi Sir,

 

Please see my reply below:

 

1. I’m connecting DDR3L memory with 1,35 V power supply. On Arria 10 GX memory banks are supplied with 1,35 V. In Quartus 18 project there’s altera_emif module, witch has these settings on FPGA I/O tab:

- protocol: DDR3

- voltage: 1.35 V (DDR3L)

- PLL reference clock I/O standard: LVDS with On-Chip Termination.

 

Clock source has LVDS output and it’s connected to dedicated clock input in hard memory controller. Whole project compiles without errors, however I’m wondering:

- usually LVDS on Altera devices requires 1,8 V bank voltage to achieve common mode voltage Vcm=1,25 V. Here I have receiver in 1,35 V bank – is this still compatible with LVDS?

 

LVDS input is power up by VCCPT which equal to 1.5V that is similar to all I/O standard. The output come from VCCIO which is 1.8V. You can refer to “Intel Arria 10 I/O Standards Voltage Levels” (page 104) for more details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd...

 

2. My clock source cannot achieve Vcm=1,25 V, it has Vcm =0,9 V and 400 mVpp swing. Is it compatible with PLL refclk input on hard memory controller with LVDS input and 1,35 V bank supply?

Since you are using the LVDS input 1.5V, so you need to meet Vcm=1.25 V in order to meet the LVDS input volatage. This is the specification for Differential I/O Standards.

 

3. I cannot find any information about internal bias of pll refclk input on hard memory controller in Arria 10 GX. I’m using DC connection between clock and FPGA and I like to use on chip termination. Does “LVDS with On-Chip Termination” for PLL refclk input mean that there’s 100 Ohm parallel termination and no bias?

Yes, you are absolutely correct. LVDS with On-Chip Termination for PLL refclk input support 100 Ohm parallel termination with no bias.

 

When I tried simulation with IBIS model generated from Quartus this input had internal bias (when separated on AC link), however most documentation on LVDS in Intel FPGAs states, that LVDS I/O’s have no internal bias.

As I mentioned before for LVDS I/O’s there is no internal bias. However for LVPECL AC-Coupled External Termination we do support termination with bias. For more details, you can refer to Arria 10 Handbook (page 147)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd...

 

Hope this helps

 

Thanks and have a nice day

 

Best regards,

NAli1

RFrac
Beginner
27 Views

Thanks for replay.

 

"LVDS input is power up by VCCPT which equal to 1.5V that is similar to all I/O standard. The output come from VCCIO which is 1.8V. You can refer to “Intel Arria 10 I/O Standards Voltage Levels” (page 104) for more details."

 

I see now that for input VCCPT matters, not VCCIO. So it will stick to the standard. To be exact VCCPT of Arria 10 is 1,8 V, not 1,5 V.

 

"Since you are using the LVDS input 1.5V, so you need to meet Vcm=1.25 V in order to meet the LVDS input volatage. This is the specification for Differential I/O Standards."

 

I'm not convinced by this because there's no toleration included. So how close one should be to 1,25 V Vcm? In Arria 10 datasheet on LVDS there’s an Vicm(DC) (V) that has min 0 V, max 1,85 V for lower data rate. Is this proper range for input common mode voltage for refclk in hard memory controller?

Also if you take a look on Arria 10 development boards it looks like there’s DC link from Silicon Labs clock source to hard memory controller. This kind of clock can’t achieve Vcm of 1,25 V with it’s power supply (however on development boards there are external terminations, so OCT is not used). 

 

 

"As I mentioned before for LVDS I/O’s there is no internal bias. However for LVPECL AC-Coupled External Termination we do support termination with bias. For more details, you can refer to Arria 10 Handbook (page 147)".

 

f there's no bias why Quartus generated IBIS model behaves like there’s one (with OCT enabled)? Also keep in mind, that we’re talking on hard memory controller, not LVDS I/O. It does not support LVPECL as clock source standard at all (emif in Quartus 18.0 Pro possible standards: LVDS OCT, LVDS no OCT, SSTL-135) . Hard memory controller input may be very different that standard I/O pll input. Also there was a discussion here https://forums.intel.com/s/feed/0D50P00003yyRRdSAM?language=en_US with conclusion that enabling OCT on LVDS will bias AC links. So I’m bit confused.

 

 

RFrac
Beginner
27 Views

Thanks for replay.

 

"LVDS input is power up by VCCPT which equal to 1.5V that is similar to all I/O standard. The output come from VCCIO which is 1.8V. You can refer to “Intel Arria 10 I/O Standards Voltage Levels” (page 104) for more details."

 

I see now that for input VCCPT matters, not VCCIO. So it will stick to the standard. To be exact VCCPT of Arria 10 is 1,8 V, not 1,5 V.

 

"Since you are using the LVDS input 1.5V, so you need to meet Vcm=1.25 V in order to meet the LVDS input volatage. This is the specification for Differential I/O Standards."

 

I'm not convinced by this because there's no toleration included. So how close one should be to 1,25 V Vcm? In Arria 10 datasheet on LVDS there’s an Vicm(DC) (V) that has min 0 V, max 1,85 V for lower data rate. Is this proper range for input common mode voltage for refclk in hard memory controller?

Also if you take a look on Arria 10 development boards it looks like there’s DC link from Silicon Labs clock source to hard memory controller. This kind of clock can’t achieve Vcm of 1,25 V with it’s power supply (however on development boards there are external terminations, so OCT is not used). 

 

 

"As I mentioned before for LVDS I/O’s there is no internal bias. However for LVPECL AC-Coupled External Termination we do support termination with bias. For more details, you can refer to Arria 10 Handbook (page 147)".

 

f there's no bias why Quartus generated IBIS model behaves like there’s one (with OCT enabled)? Also keep in mind, that we’re talking on hard memory controller, not LVDS I/O. It does not support LVPECL as clock source standard at all (emif in Quartus 18.0 Pro possible standards: LVDS OCT, LVDS no OCT, SSTL-135) . Hard memory controller input may be very different that standard I/O pll input. Also there was a discussion here https://forums.intel.com/s/feed/0D50P00003yyRRdSAM?language=en_US with conclusion that enabling OCT on LVDS will bias AC links. So I’m bit confused.

 

 

NurAida_A_Intel
Employee
27 Views

Hi Sir,

 

Please accept my apology for misunderstanding your inquiry previously. Here is my latest reply.

 

1. I’m connecting DDR3L memory with 1,35 V power supply. On Arria 10 GX memory banks are supplied with 1,35 V. In Quartus 18 project there’s altera_emif module, witch has these settings on FPGA I/O tab:

- protocol: DDR3

- voltage: 1.35 V (DDR3L)

- PLL reference clock I/O standard: LVDS with On-Chip Termination.

 

Clock source has LVDS output and it’s connected to dedicated clock input in hard memory controller. Whole project compiles without errors, however I’m wondering:

- usually LVDS on Altera devices requires 1,8 V bank voltage to achieve common mode voltage Vcm=1,25 V. Here I have receiver in 1,35 V bank – is this still compatible with LVDS?

 

It’s NOT compatible with LVDS. Your receiver has to be 1.8V. If you want to interface between 1.8 V with 1.35 V then you may have to do DC bias at board level on your own.

 

2. My clock source cannot achieve Vcm=1,25 V, it has Vcm =0,9 V and 400 mVpp swing. Is it compatible with PLL refclk input on hard memory controller with LVDS input and 1,35 V bank supply?

 

Yes, it’s compatible but your Dmax need to be less than 700Mbps.

 

3. If there's no bias why Quartus generated IBIS model behaves like there’s one (with OCT enabled)? Also keep in mind, that we’re talking on hard memory controller, not LVDS I/O. It does not support LVPECL as clock source standard at all (emif in Quartus 18.0 Pro possible standards: LVDS OCT, LVDS no OCT, SSTL-135) . Hard memory controller input may be very different that standard I/O pll input. Also there was a discussion here https://forums.intel.com/s/feed/0D50P00003yyRRdSAM?language=en_US with conclusion that enabling OCT on LVDS will bias AC links. So I’m bit confused.

 

Yes sir, you are absolutely right that we do not support LVPECL in EMIF. What I meant before about the LVPECL is just a sharing.

 

Thanks

 

Regards,

NAli1