My design's master clock is phase-locked to an external reference tone. The reference clock may be disconnected then reconnected. It's always approximately the same frequency, while the phase of the reconnected clock signal is arbitrary.
The design must recalibrate two IOPLLs plus native_phy_pll and native_phy_tx after the reference clock has been reconnected.
Unfortunately, the pointers embedded in Quartus 18.1 to the user guides for Partial Reconfiguration Intel FPGA IP (alt_pr) and altera_pll_reconfig are invalid; these IP cores appear no longer to be supported.
Please provide current information that will enable us to accomplish the straightforward objective of recalibrating sensitive circuits after power-on and after their reference tones have stabilised.
Hopeful thanks --todd
It looks like the answer is to instantiate the PHY modules (PLL, rst ctrller, and PHY) inside Qsys as Nios MM slaves. Write to address 0x100 of the high-speed PLLs to initiate calibration. I hope ...