Arria 10 IOPLL Dynamic Phase Shift using M-Counter

[FvM]

Hello,
we use to perform clock fine tuning with Cyclone designs by applying continuous phase shift  to M counter (PLL feedback clock divider). This way the frequency of all PLL output clocks is tuned by a proportional factor, similar to using a VCXO reference oscillator.

According to Arria 10 IOPLL documentation AN728, dynamic phase shift isn't provided for M-counter, so we would need cascaded PLLs to implement the intended tuning of multiple PLL outputs.

While testing an Arria 10 cascaded PLL design, I found that undocument value cntsel = 5'b01011 performs M-counter phase shift as available for Cyclone III, IV, 10 LP and MAX 10. 

Are there any reasons why the feature isn't documented?

Best regards

Frank

[Farabi]

Hi Frank,

Let me check with engineering on this. Did the phase shift you performed via M-counter is stable?

How long the PLL can get to Locked status after you performed the phase shift?

regards,

Farabi

[FvM]

Hi Farabi,
thanks for your interest.

PLL is staying locked after M-counter phase shift, Arria 10 IOPLL is behaving the same as Cyclone 10 LP which provides M-counter dynamic phase shift as documented feature.

Regards
Frank

[Farabi]

Hi Frank,

Noted. That is good info. I will update this to engineering.

regards,

Farabi

[Farabi]

Hello Frank,

I am sorry to keep you waiting. I have filed request report to engineering.

case number : 15016334401 (internal access only).

Engineering will update AN728 in future, but we still cannot confirm the schedule.

I will file KDB for temporary workaround for this setup.

regards,

Farabi

[Farabi]

Hi Frank,

I am transferring this case back to community for continuous support. I will set this case to close pending. If you have new request, please file new ticket, we will be happy to help.

regards,

Farabi