LVDS Interface in Cyclone V 5CEBA7F27C8N

[ShivaKi]

Hello,

1. In Cyclone V 5CEBA7F27C8N, if an IO pin is configured to operate as Output in 'LVDS IO Standard',

what will be the output drive current strength of that IO pin? 

2. If LVDS IO standard is selected for a IO pin, FPGA considers operating the IO pin at 2.5V LVDS?

Note: In CycloneV Device Handbook Volume 1: Device Interfaces and Integration, in Table 5-25: Programmable Current Strength Settings for Cyclone V Devices, the LVDS I/O standard is not defined.

[FvM]

Hi,
LVDS current strength is specified by the standard, standard value is 3.4 mA. Cyclone V datasheet specifies an Vod range which relates to 2.5 - 6 mA.

LVDS IO standard requires a bank VCCIO voltage of 2.5 V.

[ShivaKi]

Hello,

Related to Question 1 response, for example, a FPGA IO pin(pair) to be used as LVDS Differential Transmitting signal purpose, What is the I/O Standard to be selected for this differential pair pins in Pin Planner Quartus Prime software?

Is it LVDS or SSTL-2 Class I ? Please confirm

[AqidAyman_Intel]

I think it should be LVDS chosen as the I/O Standard in the Pin Planner in that case.

[ShivaKi]

Hello,

When LVDS I/O standard is chosen in pin planner, the drive strength field not showing any output current value. It is Blank.

Please confirm, whether the IO pin for LVDS Standard is configured as output, will the pin drive any current ?

[AqidAyman_Intel]

Yes, you are right.

There are no output current settings for LVDS IO standard. However, you could set the VOD for LVDS.

[FvM]

Programmable Cyclone V LVDS Vod (low, medium, high) relates to current strength. For full information, refer to IBIS files. You can plot output characteristics with a viewer.

[AqidAyman_Intel]

Yes, it is correct statement from @FvM. You can get the IBIS model for CYclone V from the link below:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html

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