Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19197 Discussions

Arria 10: Packing 2 Multipliers per DSP

Altera_Forum
Honored Contributor II
872 Views

The docs claim each DSP contains 2 18x19 multipliers. How does one actually use each multiplier? I created two 8b integer multiplies (8x8=16b). This should be easy to fit into a single DSP. I tried both inference and instantiating LPM_MULT. In both cases it resolved to 2 DSP. 

 

It may just decide not to pack since the resources are plentiful. However, I will need it in my final implementation - how does one coax 2 Muls/DSP?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
99 Views

Note that I also tried sharing a multiplicand between the two MULs - no joy.

Altera_Forum
Honored Contributor II
99 Views

I found this quote in the Intel FPGA Integer Arithmetic IP Cores User Guide, 17.1: 

 

"If multiple Intel FPGA Multiply Adder or ALTERA_MULT_ADD IP cores occur in a design, the functions are distributed to as many different DSP blocks as possible so that routing to these blocks is more flexible. Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device."
Reply