Are there any further documentation on how to setup CPU1 on the Arria 10 SoC or even an example project?
Here are more details.
He is thinking about starting to use the second CPU (CPU1) on our project that uses the Arria 10 SoC. He is currently running a baremetal application on the first CPU (CPU0). Separate applications would run on each core, with minimal interactions between them (AMP). He is planning to edit the linker scripts to divide the OCRAM and SDRAM into two sections, such that memory allocated to CPU0’s application is separate from memory allocated to CPU1’s allocation.
Unfortunately, he can’t find too much information about CPU1, other than that it is released from reset in user software:
https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Run-CPU1-on-Arria10-SoC-FPGA/m-p/1307718
From what he has read, CPU1 will start running at the reset exception vector. That points to several sections of startup code (such as __cs3_start_c), and eventually our application for CPU0. It isn’t clear to him how to get the CPU1 running its own startup code and application instead, as he don’t want CPU1 to run the startup code that sets up data sections, constants, stack, etc for CPU0.
