Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18981 Discussions

Arria 10 SoC EMIF Input clock jitter requirment

TSege1
Beginner
432 Views

I am designing a new board with Arria 10 SOC.
This FPGA is connected on board to two DDR4 16Bit components.
I found in Intel UG-20115 doc "External Memory Interfaces Intel Arria 10 FPGA IP User Guide" page 205 the following requirement for the EMIF reference jitter:
"The clock source of the PLL reference clock must meet or exceed
1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER"
Usually in clock source component’s data sheets the clock jitter RMS is specified for specific frequency bands for example 200kHz to 20MHz, 100kHz to 20Mhz,12kHz to 20MHz, Etc.
Can you please explain to what frequency band is UG-20115 doc Jitter RMS requirements (1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER) defined?

0 Kudos
5 Replies
yoichiK_intel
Employee
404 Views

Hi

The jitter requirements come from full band jitter value.

If you probe the PLL reference clock by oscilloscope the equipment will measure the full band jitter with Pk to  Pk and RMS parameters.

 

TSege1
Beginner
397 Views

Thank you for your reply

I know the jitter performance of my reference clock. I have a datasheet for it that states it clearly.

I am trying to understand what the requirements are to make sure that my reference clock is adequate.

Could you explain what are the jitter requirements for the reference clock? Where do these requirements come from? Are they written in some spec.?

Are the jitter requirements dependent on DDR4 data rate?

 

Regards,

yoichiK_intel
Employee
391 Views

Hi

Jitter amount affects the timing margin in the IP.   If the reference clock has more jitter than requirement there may be malfunction on the IP due to the timing issue.  The jitter requirement is consistent regardless any DDR4 data rate.  

TSege1
Beginner
291 Views

Thanks,

For Arria 10 I use LVDS 133MHz as reference clock for the DDR4 controller with 0.37pSec typical RMS jitter (Integration over 0.1MHz-20MHz frequency band)

The spec for the Arria 10 as defined in Intel EMIF Arria® 10 FPGA IP User Guide, page 205 is 1.22ps at 1e-16 BER , Identifier: PHY_DDR4_REF_CLK_JITTER_PS.

Please advise if OK

tamir,

yoichiK_intel
Employee
288 Views

Hi

Your reference clock jitter should be no problem to the Arria10 reference clock jitter spec.

Reply