Hi,
I'm in the early-early stages of capturing a schematic for a design that will use an Arria 10 SX 066 SoC.
I'm working on the DDR3 interface at the moment. I will be using an X16 DDR3 configuration with ECC, (so three DDR3 SDRAMs).
I’m trying to reconcile the Arria 10 external memory pin information table from the Altera website with what I see connected in the A10 SoC development board schematic which I'm using as a reference. Both documents are attached here.
What I see in the development board schematic seems to conflict with the external memory pin table.
For example; command address A0. According to the external memory pin table, regardless of what DDR configuration you’re using, A0 must always go on bank index 12.
However, in the development board schematic, (HPS DDR connections on sheet 19), A0 is connected to pin B26, (which is Bank 2K index 44).
What I see in the development board schematic seems to conflict with the memory interface pin table across the board. Am I misinterpreting something here?
Thanks,
Jason
