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Altera_Forum
Honored Contributor I
1,514 Views

Arria 10 auto configuration issue with EPCQ-L

Hi experts, 

 

I come across a serious issue on my Arria 10 board, using 10AX016C4. Flash memory is EPCQ-L256 

When I wrote program using jic-file with USB Blaster 2, some jic-file, call as "A.jic" here in after, caused auto configuration issue. 

 

Once programming and verify have completed successfully, but after power off-on, auto configuration failed. Configuration has not done, and this was mysterious symptom though , JTAG-TDO port has become TDI through port, no clock delay, exact same with TDI. 

 

As I cannot use JTAG port, because TDO doesn't run correctly, I erased EPCQ-L by Active Serial port. Then TDO port became Hi-Z correctly after next Power off-on. And I wrote A.jic again, the result was same, TDO fail. 

 

But I wrote another jic-file, call as "B.jic" here in after, then auto configuration has done and my program in Arria 10 ran correctly. After that, I write A.jic file again, then auto configuration has done and my program ran correctly. And after that A.jic file writing has been always fine. 

 

I have three boards, and I checked two boards ran correctly by this writing manner above, writing B.jic. And I still have one failed board, not writing B.jic. 

 

I extracted program data from EPCQ-L by Examine function via Active serial port, and I found each pof-files in three boards, two fine and one fail, were exact same. So I believe program file in EPCQ-L and EPCQ-L itself should be fine. 

 

It looks 10AX016C4 issue, but very strange symptom. 

 

Does anyone have any idea? 

 

Thanks, 

Tetsuya
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12 Replies
Altera_Forum
Honored Contributor I
73 Views

Hi Tetsuya, 

 

Did you try to perform a full erase to the EPCQL256 first before programming any .jic file? Is there any difference in the between A.jic file and B.jic file? Perhaps you can check the project design settings between A.jic file and B.jic file.  

 

Regards, 

nyusof 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
73 Views

Hi nyusof, 

 

Thank you for inquire. 

 

I have erased EPCQL by Quartus programmer's erase function via AS port before writing. Is there any other "full" erase function? 

 

The revisions of building programmer are different among A.jic and B.jic. 

A.jic was built on Standard edition 16.1.1, a bit old, and B.jic was built on Lite edition 17.0.0. 

And checking the both of jic files by Binary editor, there is some difference. Behind the first header, describes Quartus revision, device type and so on, it appears "6A 6A 6A 6A". And before this unique code, 

A.jic describes "FF FF FF FF ... FF FF 6A 6A 6A 6A". 

B.jic describes "... C1 9E CE 1E E1 FC 2A 00 6A 6A 6A 6A". (not FF FF...) 

As I have no idea about jic file data format, I couldn't see the meaning of this difference. 

 

And my point of view on this issue. 

1. Can jic-file (or pof-file in EPCQL) control JTAG-TDO port on the way of auto configuration? 

2. Is it possible to make TDI though out mode on TDO, without shift clock delay? 

3. Why does it run correctly even on A.jic after writing B.jic?  

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Hi nyusof, 

 

I add information. 

As I described, there are three board. Two of them are fine by B.jic writing and one is bad, not writing B.jic. 

When I extract pof data of them via AS port, the data after writing A.jic are exact same among them. 

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Hi tetsuya, 

 

1. Are you sure A.jic and B.jic you generated all using the same settings likewise in picture? Including all tabs? 

2. It seems like you go so far and started to compare both jic files using hex editor to get the difference without making sure all settings between A.jic and B.jic look perfectly same. 

3. Please provide the settings you chosen before go next step asking latest question you posted. JTAG should not be unable to be programmed if you are in the correct settings. 

4. Between, I have tried notepad++ which completely cannot decrypt, and notepad neo which able to see only first few lines info likewise you said, however, it is not possible to read encrypted binary data, so no point comparing in this method. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
73 Views

Hi Tzi Khang, Lim, 

Although B.jic file was built by myself, A.jic file was built by another outsource. The both of jic files were generated from same sof-file. I would ask to the outsource about setting. 

But once I was explained the building manner from them, there was not any wrong process. 

 

Anyway I would ask. 

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Hi Tzi Khang, Lim, 

By the way, as I mentioned above, the both jic files were generated from same sof-file and it is used only "Convert Program Files" of programmer for building jic-file. And there are not so many options. Is it good enough to compare the setting of "Convert Program Files"? 

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Hi tetsuya, 

I believe you stuck somewhere here, thus I lead you towards 

https://www.altera.com/en_us/pdfs/literature/an/an370.pdf (https://www.altera.com/en_us/pdfs/literature/an/an370.pdf

Direct refer pg9 is stating the condition for multiple configuration. 

 

I simplify the elaboration: 

It depends on data size, configuration device required, and note: The Quartus II Convert Programming File tool creates a .jic file based on the setting you set. Configuration will fail if the wrong configuration device type selected in the Convert Programming File tool. However, configuration will work if you have more configuration devices on your design compared to your settings in Convert Programming File tool. 

 

This shall solve your problem. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
73 Views

Hi Tzi Khang 

 

Thank you for your advice. 

 

My design occupies only 30% of Arria 10 device. Is it related to this matter on AN370? 

 

Back to my question, A.jic file does not always cause failure. Once B.jic file has been written, after that, I can use A.jic file also without any failure. So A.jic file might be some trigger for FPGA malfunction, however another cause would be there. 

 

Especially TDO port failure, TDI throughout, is strange symptom. Can bad program file affect to dedicated JTAG port? Although I have been checking Altera-Intel documents, I have not find such throughout mode on TDO-JTAG so far.  

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

All, 

I have just heard information about this matter from outsource who created A.jic file. They use some unique original batch file for generating jic-file. And the jic-files caused this issue. Now I inquire the setting for the jic in the batch to them. 

 

I have confirmed the data on binary editor and found some unique code appeared before ゙6A 6A 6A 6A゙ in the file which was created by batch. 

 

Regards 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Experts, 

I have gotten further information about the batch file. It was written in script and they referred the both of documents below. Does it work even on the current program file? 

 

https://www.altera.co.jp/support/support-resources/knowledge-base/solutions/rd10132010_126.html 

AN736 

https://www.altera.co.jp/documentation/suc1427659050061.html 

 

Regards, 

Tetsuya
Altera_Forum
Honored Contributor I
73 Views

Hi Tetsuya, 

Escalated to Nios section. Please post it to Nios. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
73 Views

Hi Tzi Khang, 

Thank you for your suggestion. I have posted this article to the Nos forum as thread below. 

 

https://alteraforum.com/forum/showthread.php?t=57075&p=232235#post232235 

 

Best regards, 

Tetsuya
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