Arria 10 clock problem

[Altera_Forum]

Hello, 

Im implementing a custom design using Arria 10 (10AX115N4F40I3SG). During Place and Route, the following problem related to clock asiignement appears: :confused:  Error (179009): Could not find enough available I/O pin locations that supports the Current Mode Logic (CML) standard (2 locations affected) Info (175029): AJ5 Info (175029): pin containing PIN_AJ5  The clock im using is mapped to the input PIN_AJ5 of the FPGA on the board. I even checked this PIN in the FPGA pins document and it's a clock input. Does anyone had a similar problem using Arria10? :confused::confused: note:  - Im using Quartus v14.1. - This clock is mapped in internal PLL in my design.

[Altera_Forum]

Hi, you will get this error might due to you have constrained an I/O pin or group of pins to a location, bank, or region that could not support the required I/O standard. 

You have to make sure that you have not assigned pins requiring a particular I/O standard to banks that do not support the standard, and that you have not constrained too many I/O pins requiring a particular voltage to a region that does not have enough I/O pin locations capable of supporting the selected voltage.

[Altera_Forum]

As I understand it, the CML IO standard is for transceiver refclk but not normal clock input. Just wonder if the pin_aj5 that you are using is a transceiver refclk pin?

[Altera_Forum]

--- Quote Start ---  Hello, Im implementing a custom design using Arria 10 (10AX115N4F40I3SG). During Place and Route, the following problem related to clock asiignement appears: :confused:  Error (179009): Could not find enough available I/O pin locations that supports the Current Mode Logic (CML) standard (2 locations affected) Info (175029): AJ5 Info (175029): pin containing PIN_AJ5  The clock im using is mapped to the input PIN_AJ5 of the FPGA on the board. I even checked this PIN in the FPGA pins document and it's a clock input. Does anyone had a similar problem using Arria10? :confused::confused: note:  - Im using Quartus v14.1. - This clock is mapped in internal PLL in my design.  --- Quote End ---    I did a quick check with my Quartus II 15.0 on your device, the pin AJ5 is a normal clock input pin but not transceiver refclk pin. You can try to use other IO standard ie LVDS, LVPECL to see if can pass the compilation.

[Altera_Forum]

Hello, 

Thank you for your replies. In fact, as bfkstimchan said the pin AJ5 is a normal clock. I even tried 3 others clock inputs and I still have the same problem. Anyway, since this clock input feeds an internal PLL in my design (Altera normal PLL IP), i replcaed this PLL with Altera IOPLL IP. The problem is solved! I think that the error is related to the placement of the normazl Altera PLL during Plca e and Route phase. Thnak you all for your help. Best regards.

[Altera_Forum]

Just to add on, each bank have 4 dedicated refclk, but only 1 (any) of the 4 can reach the bank's IOPLL. 

Also, you cannot connect bank A refclk to bank B IOPLL. From what I know Arria10 IOPLL is different from the past devices. They are not arranged as center/corner PLLs.

[Altera_Forum]

--- Quote Start ---  Hello, Thank you for your replies. In fact, as bfkstimchan said the pin AJ5 is a normal clock. I even tried 3 others clock inputs and I still have the same problem. Anyway, since this clock input feeds an internal PLL in my design (Altera normal PLL IP), i replcaed this PLL with Altera IOPLL IP. The problem is solved! I think that the error is related to the placement of the normazl Altera PLL during Plca e and Route phase. Thnak you all for your help. Best regards.  --- Quote End ---    Glad to hear that you have managed to resolve your issue and thanks for sharing the resolution.