Arria 10 configuration: Linux Altera Passive Serial SPI FPGA Manager

[Rams]

Hi,

We are planning to use Arria 10 FPGA with NXP LX series of processors.  We want to test FPGA loading from U-boot and linux through spi bus.

With reference to the documentation

https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt

&dspi1 {
status = "okay";

fpga_mgr_spi: fpga-mgr@0 {
compatible = "altr,fpga-arria10-passive-serial";
spi-max-frequency = <20000000>;
reg = <0>; 
nconfig-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
nstat-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
confd-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
status = "okay";
};
};

It is not clear how to program the fpga using passive serial.

Please clarify

[KennyTan_Altera]

Sorry for the late reply will get back to you as soon as we can.

[aikeu]

Hi Rams,

May I know more details on how your boot up progress setup?

Are you booting from QSPI or SD card or?

Are you going to load the FPGA from a different storage through SPI after intial boot up from a default storage location in order to load the FPGA program?

The document that you refering to is part of Linux, normally loading the FPGA is before starting Linux.

Correct me if my understanding differ from you request.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Rams,

Any follow up with the previous comments?

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Rams,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks.

Regards,

Aik Eu