Arria 10 transceiver PLL spacing

[Thorsten_S]

UG-01143, section 3.1.1 states several spacing constraints on ATX and fPLLs which operate at the same VCO frequency.

What happens when these constraints are violated (apart from Quartus issuing a critical warning)?

Are there any means to quantify the PLL/transceiver performance in this scenario (i.e. when PLLs are too close)?

[Deshi_Intel]

Hi,

I don't have the full detail but we have seen issue in the past that noise coupling effect may occurs that caused increased jitter in neighboring transceiver channel when PLL spacing requirement is violated.

There is no good way to quantify the coupling effect hence came the design guideline to follow the PLL spacing requirement to avoid putting user design at risk.

Thanks.

Regards,

dlim