I'm designing in an SO-DIMM with an ArriaGX (EP1AGX35DF780C6N). The 780 pin Arria GX must use both the top and bottom banks to support the 64-bit SO-DIMM interface. This requires that the top banks (3,4) use the top DLL and PLL5 while the bottom DLL and PLL6 should be used by the bottom bank (6,7).
I have some questions i hope someone could answer:
1) The EMI handbook states that only Arria II GX supports top+bottom banks in the same DDR2 interface. Can anyone confirm that this also applies to Arria GX?
2) If i feed the same external clock to both PLL5 and PLL6 dedicated input pins, will the resulting PLL output clocks (200 MHz) be phase aligned (for DQS block purposes)?
3) The SO-DIMM requires three pairs of CK/CK# clock signals. Can these clocks be driven by the same PLL? Would this not introduce skew since the clock paths would originate from one side of the device while signals synchronized to the clock (address and command groups) would originate from another side of the device?
Could anyone provide an example of a DIMM design for Arria GX? I'm looking at Arria II GX but this device is quite different in many respects.
Thanks.
