Dear all,
I use ArriaV FPGA. On FPGA, I have a bi-directional bus which can be used in asynchronous and DDR mode.
In DDR mode, I use DQs (Data strobe) to synchronize data for read request.
I want set manually the delay (D3_1) to read correctly the input data because the delay depend of the using clock .
When I use the assignement editor, i have this warning is appear:
I set DQS pin with D3 Delay (I/O buffer to internal cells) with 4 value.
Critical Warning (176425): Ignored Input Delay from Pin to Internal Cells logic option assignment (setting = 4) to input or bidirectional pin DQS because all of its fan-outs already have assignments of a different delay value (setting = 0).
In the compilation report, D3_0 is equal to 0.
Then I use RPE tool and on the DQS PAD, I set the 4 value in D3 Delay Chain 0. After I click on the check and save all netlist changes. Quartus run Fitter and assembler. There is no warning and error.
In the compilation report, I don't have access to delay chains report. I'm not sure that Delay chains are programmed correctly.
Do you have any idea to set properly the delay timing D3_0?
Thanks in advance for your help.
