Arria V interfacing LVDS 2.5 with 3.3V reciever

[Altera_Forum]

Hello, 

 I just wanted to check if there are likely to be any problems interfacing the following clock fanout ( http://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v IO on the arria V. The differential specifications seem fine. My concern is with the "Fail Safe" 300k pull-ups on the Receiver. that will pull the lines high when not driven. Although this doesn't exceed the absolute maximum io voltage of 3.6 in the device datasheet, it is outside the common mode value specified for 2.5VLVDS on the device. When enabling the LVDS driver on the Arria V, the lines will briefly be at 3.3 volts. Could this be a problem?

[Altera_Forum]

Hi rmawatson, 

 When interfacing the Arria V LVDS output with other receiver, you would need to ensure the VCM of the LVDS buffer still within the specification ie 1.25V. If out of the spec, then you might want to consider using AC coupling to reconstruct the VCM to meet the specification to avoid any issue to the device.

[Altera_Forum]

--- Quote Start ---  Hello,  I just wanted to check if there are likely to be any problems interfacing the following clock fanout ( http://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v IO on the arria V. The differential specifications seem fine. My concern is with the "Fail Safe" 300k pull-ups on the Receiver. that will pull the lines high when not driven. Although this doesn't exceed the absolute maximum io voltage of 3.6 in the device datasheet, it is outside the common mode value specified for 2.5VLVDS on the device. When enabling the LVDS driver on the Arria V, the lines will briefly be at 3.3 volts. Could this be a problem?  --- Quote End ---    You can refer to the following KDB solution for further details:  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01242007_248.html  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04282010_33.html

[Altera_Forum]

hi rmawatson, 

 bfkstimchan is correct, typically just need to make sure the it meets the 2.5V lvds Vicm and Vod.   Also in the datasheet it was mentioned that the difference in the Vicm could have data rate limitation. It is in the datasheet :p

[Altera_Forum]

Hi, thanks for the replies. I came across the 2 KDB's before, and it makes perfect sense. My only confusion is with the failsafe pullups in the buffer. Basically, as far as the actual differential driver and the receiver goes, the common mode of the Arria V device and differential levels are well within the spec of the receiver.  

 My concern was really just about the point at which the Arria V enables the LVDS output. On power up the TI buffer will be pulled up as the Arria V ouputs will be high impedance until it is configured and the LVDS outputs are enabled. At this moment the lines will be very weakly pulled to 3.3V by the buffer's 300k resistors. Obviously the low impedance LVDS driver of the Arria V will drive its desired common mode voltage when it is switched on, and overcome these pullups. But at this moment of being switched on, there will be 3.3v at the Arria V device pins. My concern is whether this might cause any issues to the driver. the 3.3 v is well within the absolute maximum (3.6) of the device pins, but I don't know if there is any problem at all with the differential driver of the Arria V seeing 3.3v on the pin when it is switched on.  This all seems unlikely that there will be any issues, but I'd rather not AC couple if this is not necessary.  Thanks again!