I am designing a DDR4-32bit interface for Arria10.
I will use either a GX220 or a GX270 device with F29 package.
I have to decide to use 'Package deskewed with board layout' or not.
The package delays reported in the pin file for the same signal betwen GX220 and GX270 differ slightly. I checked the dq/dqs pins and found 0 to 14ps delay difference comapring GX220 to GX270.
When I choose to compensate the package skew by external trace length for GX220 and then mounting a GX270, then the HMC has to compensate this 14ps mismatch by shifting the signal durcing calibration.
My question is:
a) How much total skew difference can be compensated by the deskew calibration shift during DDR4 calibration ?
b) I have seen up to 80ps package delay difference between DDR4 signals. When not ticking the box "Package deskew with board layout" Quartus takes care about package skews internally. Are the package skew differences deskewed using the same FPGA resouces as calibration shift ?
thanks for your detailed answer, I just haven't recognized the section 2.8.6 in emi_plan.pdf.
I checked board deskew just in ug_emif.pdf , sorry.
I am wondering if this would work, too:
1) Fit the design for device A with board deskew ticked. Adjust the trace length on PCB.
2) Generate a report for the package skew differnces between device A and device B.
3) Apply sdc timing constraints set_output_delay() for device B using the delay differences between the packages.
This should replace the step
"6. Calculate board skew parameters, only taking into account the board traces for device B, and enter that value into the parameter editor for device B."
4) Fit device B with board deskew ticked.