Thank you for reaching out to Intel FPGA Community. According to Intel® Arria® 10 Device Datasheet, this device have different common mode voltage for different I/O Standards available.
For LVDS, the input common mode voltage (Vicm) is maximum at 1.6V and 1.85V. You can refer to Table 18 and Table 19 to see the Vicm and Vocm values for other I/O standards.
I am using Arria 10 FPGA my design. My application is USB (Host and device) and DP (Source and sink). I am using the Transceiver bank for the USB and DP interface and I have a few queries in it.
1. When FPGA is in DP Sink or USB Device [Receiver] mode will there be any common-mode voltage or bias voltage to the Multiplexer IC [TMUXHS4412] from the FPGA.
I'm muxing the USB and DP Signals via these mux to the USB - C Connector. Please find the attached block diagram.
2. What is the common-mode voltage of the transceiver bank in Source and Sink USB or DP IP?
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