I have designed a board with Arria10 FPGA (10AX057N2F40E2SG), Totally we have 5 boards manufactured, and in that 3 boards have this issue. I can able to program the FPGA, In the Quartus prime tool programming is 100% succeded but the config_done LED is not coming up. Sometimes it is blinking. Arria10 FPGA power sequence is controlled by the LTC2977 power sequencer. I have tested with the same power sequencer code used for all 5 boards and the same FPGA programm.
But one major difference is I'm using every interface integrated FPGA code JIC for programming but the same SOF is working perfectly. I have different JIC files for each interface (Standalone) but that is working perfectly.
I'm not able to find a solution for this pl help with your thoughts.
Pl, check the attached video of the config_done LED status. Just for reference.
Sorry i am not able to view the video with some technical difficulty. Just want to clarify from you. Is all the 5 boards having the same schematic and also same programming file? Other than config_done, can you probe other configuration pin?
I have different programming files (.JIC) for example LED Blinking, Some IO+ PCIe+DDR, and Full IO utilized JIC. In this only with Full IO including DDR,PCIe,SERDES utilized program JIC is only not working on 3 boards. but the same sof is working.
Thanks for the information. It sounds like the flash could have issue as SOF is working fine. Can you please check on the data bus and see if anything coming from/to the flash?
Another thing is that, what is the resources utilization in quartus compilation report for full design?
Here is the details from the fit.rpt
; Total registers ; 141905 ;
; Total pins ; 365 / 812 ( 45 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 26,496,000 / 36,864,000 ( 72 % ) ;
; Total RAM Blocks ; 1,800 / 1,800 ( 100 % ) ;
; Total DSP Blocks ; 3 / 1,523 ( < 1 % ) ;
; Total HSSI RX channels ; 12 / 48 ( 25 % ) ;
; Total HSSI TX channels ; 12 / 48 ( 25 % ) ;
; Total PLLs ; 24 / 96 ( 25 % )
I have probed all the lines of Flash, The outcome is,
FPGA is trying to drive chip select, It's going low then high then repeating the same. Because of the CS pin flickering the data pin is trying to send something data, whenever the CS pin is in a low position for a small period of time.
But while probing twice the FPGA booted. but don't know how it happens.
I was suspecting the power sequencer and another configuration pin. But both are fine concluded after doing some experiments on another working board.
nCS will go LOW when configuration is happening and go HIGH when it is done. If it is toggling, that means the configuration is not done properly. The reason i ask to check on configuration pin like data0, data1, dclk, nconfig, nstatus is to determine the potential root cause. If there is no data from data pin, it could be the board trace issue or flash issue.
Another thing to check is to read out the bitstream programmed into QSPI and then compared with the preprogrammed JIC file.