We are referring to the same document. But I'm afraid they're using pClk for the entire design.
Specifically, we wanted a guide or a series of steps which will help us in taking uClk_usr signal as an input signal in hw/rtl/QSYS_IPs/avst_decimator/avst_decimator.sv file. The uClk_usr signal is present as input in hw/rtl/ccip_std_afu.sv but we are finding it difficult in order to correctly take it as input in the avst_decimator.sv file.
Path to avst_decimator.sv is:
<path to streaming_dma_afu folder>/hw/rtl/QSYS_IPs/avst_decimator/avst_decimator.sv
I am not sure about the DCP Version.
We are accessing the streaming dma afu folder by:
1. SSHing into devcloud
2. "devcloud_login" into "Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL" node
3. Performing "tools_setup" of "Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL"
4. cd "$OPAE_PLATFORM_ROOT/hw/samples/streaming_dma_afu"
The path to avst_decimator.sv is
Expanded path is "/glob/development-tools/versions/fpgasupportstack/d5005/2.0.1/inteldevstack/d5005_ias_2_0_1_b237/hw/samples/streaming_dma_afu/hw/rtl/QSYS_IPs/avst_decimator/avst_decimator.sv"
Sorry, I was looking at the wrong directory. After looking at the correct directory then I am able to find the file.
You can modify the file in ccip_std_afu.sv so that the AFU IP is using UserClk and not Pclk.
It looks like the PCIe IP is using PCLK and the AFU is running using uclk_user which is not able to match the frequency. You will need to implement clock crossing to make sure that the clock is able to pass to the AFU design without any issue.
After further checking, the rtl should not be change. You will need to modify the json file so that it is using uclk_usr. You may refer to "hello_mem_afu" example design json file.