Arria10 HPS route UART0 to FPGA.

[ONors]

I hav a SOM with an Arria10 SOC. For this SOM I have two different carrier boards. One is a evaluation board, the other is a custom made board. Unfortunately HPS UART0 is not connected to anything on the custom carrier board, so I am unable to see any output from the HPS until a full boot of Linux has completed and I can access it over SSH. Nor can I play with it in U-Boot. On the evaluation SOM i can see data on written to UART0 and play around in U-Boot. Can I access the UART through the FPGA as a temporary fix while I wait for the next HW revision? I have tried to do so in QSYS under altera_arria10_hps / Pin Mux / IP selection by connecting the UART to the FPGA in stead of the HPS and routing it to the FPGA under Advanced FPGA Placement. uart0 then shows up as a conduit, which I connect to a RS422 driver chip at top level. What I see transmitted on the UART does not look like valid data. There are several logic levels, even when no receiver or driver is connected on the receiving end. If I instead of the HPS UART connects a test signal generated in the FPGA to the RS422 driver the signal looks as expected. Any advise as to what I am doing incorrect?

[EBERLAZARE_I_Intel]

Hi,

I am kind of confused on what is happening, correct me if I am wrong, you are trying to HPS Uart0 in the custom made board as in the evaluation board? Because the custom made board HPS Uart0 is not working as expected? 

Yes you can route it, how did you generate the device tree and U-boot image/kernel image?

[ONors]

I am trying to connect UART0 to the FPGA in stead of the dedicated HPS IO and is wondering if the way I did it correct since the data I am reading on the FPGA IO where i connected the UART0 outputs is not what I was expecting.

[ONors · Accepted solution]

The strange behavior I was observing seams to have been caused by a faulty oscilloscope.