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Honored Contributor I

Arria10 PCIe DMA Capabilities

I am simulating the Arria10 PCIe DMA design that's called out in the "Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide". It uses the "ep_g3x8_avmm256_integrated.qsys" Qsys design that's located in the a10 PCIe IP directory. This PCIe design simulation uses the "Avalon-MM with DMA" application interface, internal descriptor controller and Altera PCIe BFM. The test bench has the apps_type_hwtcl parameter set to 6 = "DMA Simulation only". If you set it to 5, you should be able to do a Programmed IO (PIO) and a DMA operation. The simulation always fails on the PIO operation. Is this design only capable of performing DMA and not PIO operations? When I reconfigure the Qsys design with an external DMA controller, I can perform PIO and DMA operations.

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