Showing results for

- Intel Community
- FPGAs and Programmable Solutions
- Programmable Devices
- bpsk demodulator with phase lock

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Mute
- Printer Friendly Page

Highlighted
##

Altera_Forum

Valued Contributor III

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-24-2016
07:40 PM

719 Views

bpsk demodulator with phase lock

Hi, i want to realize a bpsk demodulator for a receiver tha is not coherent with the transmitter, so the phase of the receiver's local oscillator could be unknown.

I read about costas loop but i don't understand how to realize/simulate it. I understand that i have to multiply the input by SINE and COSINE and filter out high frequencies components. At this point i have to multiply the output of LPF. I don't know how to design the loop filter and NCO after that. Could you explain me better that kind of demodulator? Is there another way to demodulate BPSK signal?
2 Replies

Highlighted
##

Altera_Forum

Valued Contributor III

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

07-07-2016
07:46 PM

11 Views

I am also facing the same problem. Did u implement it ?

Highlighted
##

Altera_Forum

Valued Contributor III

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

07-08-2016
05:15 AM

11 Views

BPSK costas loop is a subset of Costas loop for qpsk/16qam etc.

You can design an NCO inside fpga with its accumulator incremented/decremented according to phase error(with appropriate scaling) and in the correct sense. The loop consists of two branches(sin/cos multiplied by same input). This multiplication produces a sideband that need to be filtered. The phase error is then the result of product of the the two filtered branches. The error itself needs its own filter to smooth it out and control the loop(normally an IIR filter with its cutoof controlled by alpha factor). Once the design is done it will require plenty of effort to tune the loop i.e. find out alpha that gives best loop jitter. So it is plenty of work. Moreover, in a practical receiver the clock may also need its own recovery loop. The front end of receivers requiring clock recovery and phase tracking is a formidable job but not so on block diagrams at UniFor more complete information about compiler optimizations, see our Optimization Notice.