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Hi All,
It is important for my project to understand whether the reset has happened as a result of a watchdog trigger.
I am triggering a watchdog reboot by executing
echo 1 > /dev/watchdog0
This causes a reboot, however, when reading the address 0xFFD05000 from u-boot its value is always 0.
I thought that the u-boot was resetting the values of that particular field, thus I added this code on the ./uboot-socfpga/arch/arm/cpu/armv7/lowlevel_init.S:
ENTRY(lowlevel_init)
ldr r0, =reset_manager_base_stat
ldr r9, =(0xFFD05000)
ldr r9, [r9]
str r9, [r0]
However that variable, e.g. reset_manager_base_state remains always 0.
Any ideas what I am doing wrong?
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Hi Aik,
Any information you might have collected up to now?
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Hi bntl,
Sorry for the late reply, I was on holiday leave previously.
I try to check the info from your case and was wondering is the reset manager stat register not able to change with the running lowlevel_init.S?
Can try if it can be changed using the mw cmd in uboot user space?
Are you changing the bit9 related to warmreset request in reset manager stat regsiter?
Thanks.
Regards,
Aik Eu
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Some reset sequencing documentation for Arria10 which may help:
Thanks.
Regards,
Aik Eu
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Hi bntl,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Thanks.
Regards,
Aik Eu
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Hi Aik,
I hope you are doing well and many thanks for getting back to me.
I might be able to change it but this isn't what I want. I want to read its value. This register's value should indicate which module caused the ARM reset. However, I am currently this register only reports a zero value.
FYI, I am referring to the following register:
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