Arria10 to DDR4 layout guidelines

[Itai_a]

Hi,
In Table 265. Layout Guidelines on page 253 at document " External Memory Interfaces Arria 10 FPGA IP User Guide" what does tCK stand for in Clock Routing?

Regards

[AdzimZM_Intel]

Hi,

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tCK stand for clock cycle.

Let say your DDR4 is running at 1200MHz, then one clock cycle is 0.8333ns. (1/1200MHz)

Therefore in this case, 1.5 clock cycle is 1.25ns.

Regards,

Adzim

[AdzimZM_Intel]

Hi

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Regards,

Adzim

[AdzimZM_Intel]

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