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Arria10 transceivers and CSI

AlehTS
Beginner
131 Views

Hello.

I have a task to receive data from CSI sensor.

This sensor has CSI  bus with 1 clock line and 4 data lines. Data are transferred on both edges of the clock. The clock rate is about 1.5GHz. Is is too much for normal IO pins, so I am  thinking about using transceivers.

The data does not contain embedded clock. 10b\8b or 64b\66b is not used. Long sequences of ‘0’ or ‘1’ are possible.

From transceiver PHY  user guide: the receiver portion of the PMA is comprised of the receiver buffer, the clock data recovery (CDR) unit, and deserializer. Does this mean, that it is not possible to receive data without embedded clock?

And  generally, is it possible to receive data from CSI source using transceivers?

Thank you.

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1 Solution
Deshi_Intel
Moderator
118 Views

HI,


Pls see my reply below.


  1. Does this mean, that it is not possible to receive data without embedded clock ?
  • Correct. Transceiver architecture is meant to receive data transfer with embedded clock
  1. And generally, is it possible to receive data from CSI source using transceivers ?
  • From Intel FPGA perspective, we don't support MIPI IP solution
    • So, unfortunately this is something beyond Intel support plan and you will need to explore by yourself
    • One thing that raise my concern is you mentioned long continuous of 1 or 0 data pattern transfer. This is bad for transceiver receiver architecture and it will caused CDR to loose lock. For typical high speed protocol application, it will trigger to send "IDLE" data pattern to keep the CDR locked if there is no active data transfer on-going.


Thanks.


Regards,

dlim


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5 Replies
Deshi_Intel
Moderator
119 Views

HI,


Pls see my reply below.


  1. Does this mean, that it is not possible to receive data without embedded clock ?
  • Correct. Transceiver architecture is meant to receive data transfer with embedded clock
  1. And generally, is it possible to receive data from CSI source using transceivers ?
  • From Intel FPGA perspective, we don't support MIPI IP solution
    • So, unfortunately this is something beyond Intel support plan and you will need to explore by yourself
    • One thing that raise my concern is you mentioned long continuous of 1 or 0 data pattern transfer. This is bad for transceiver receiver architecture and it will caused CDR to loose lock. For typical high speed protocol application, it will trigger to send "IDLE" data pattern to keep the CDR locked if there is no active data transfer on-going.


Thanks.


Regards,

dlim


AlehTS
Beginner
113 Views

Hi, dlim!

1. I do not plan to use ready-made IP for MIPI. I'll create it by myself.

The only thing I need from transcievers is to deserialize data.

Normally, long 0 and 1 are not a problem for CSI, because the clock is transmitted over separate line.

So, if transceiver circuitry can not be used for my purpouse, can I use simple altlvds_rx deserializer, which is connected to transccieiver pins? Transceiver pins can accept much higher frequencies, than ordinary pins.

 

2. Do I understand correctly, that the same situation is with transmitter? I mean, that tramsmitted signal always has embedded clock.

 

Thank you.

Oleg.

Deshi_Intel
Moderator
111 Views

HI Oleg,


  1. can I use simple altlvds_rx deserializer, which is connected to transccieiver pins? Transceiver pins can accept much higher frequencies, than ordinary pins.
  • No you can't.
    • LVDS IP is meant to connect to FPGA IO pins and not FPGA transceiver pins
    • Only transceiver IP is allowed to connect to transceiver pins
    • But you are right also that LVDS IP and FPGA IO pins can't operate that fast at 1.5GMHz so you can't use LVDS IP that pair with FPGA IO pins also


  1. Do I understand correctly, that the same situation is with transmitter? I mean, that tramsmitted signal always has embedded clock.
  • Correct. Both transmitter and receiver architecture are operating with embedded clock

 

Thanks.


Regards,

dlim


AlehTS
Beginner
105 Views

Thank you, dlim.

Please clarify one thing: in Arria10 the transceiver bank has 6 channels and 2 reference clocks inputs. If incoming data have embedded clock, what the reference clocks are for? 

I can suggest, that they are used by transmitter to generate high speed clock and they are compared with recovered clock in RX mode to make sure that pll is locked correctly.

May be here are some other purposes of ref_clk?

Thank you.

Best regards,

Oleg.

Deshi_Intel
Moderator
92 Views

HI,


You can always checkout below user guide doc to learn more about Arria 10 transceiver architecture.

Now to answer your question - transceiver refclk pin is used to perform following function

  • a) provide refclk to Tx PLL that used to clock transmitter Tx channel
  • or b) provide refclk to receiver Rx channel CDR
  • or do (a) and (b) together


Alright, I am now setting this case to closure.


Feel free to post new forum thread if you still have further enquiry in future


Thanks.


Regards,

dlim


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