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Transceiver arbitrary data rate

zx71769
Beginner
127 Views

Hello ,

env: Quartus 18.1   Board: Arriav V 5AGXFA5H4F35C5

I try to input parallel data and output serial data. So I choose Native PHY IP for my design.

Because I want to let it operate lots of data rate 1Gbps~6Gbps (100 Mbps/step)

So I have a idea below:

"PLL IP"  -> "TX PLL IP" -> "Native PHY IP"

I can change PLL output clock by adjusting M/N/C parameter.

TX PLL IP as I know it has fixed magnification.

Native PHY can use external TX PLL.  

---------------------------------------------

So if I want to let Native PHY operate 1000Mbps.

PLL IP can output 100M Hz clock. And I can use 10x TX PLL.

So TX PLL can produce 1000M bps. And finally  Native PHY can output 1000M bps data rate.

 

I am not sure if my thinking is right or not.

Thanks for help !!

 

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2 Replies
SengKok_L_Intel
Moderator
95 Views

Yes, you may refer to chapter 17, transceiver reconfiguration controller for more information.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf


Regards -SK


SengKok_L_Intel
Moderator
74 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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