ArriaGX compile times

[Altera_Forum]

Hi everyone, 

 I'm working on an ArriaGX-based design and have been getting obscene compile times (2-3hrs usually, 30mins-1hr w/ NO changes since last compile & full incremental compile on).  I'm using the arriaGX '50' size part in a 780 pin package and it is about 60% full logic-wise.  This makes me wonder, what kind of compile times is everyone else using the ArriaGX seeing?  Thanks, Frank

[Altera_Forum]

Seems long, but how much time is spent in: 

Analysis and Synthesis Fitter, which is broken up into:  - Placement  - Physical Synthesis  - Routing (I'm assuming the other steps are negligible.) Note that you can get placement time, physicaly synthesis time and routing time out of the fitter messages. The biggest culprit I've seen for compile times going up is physicaly synthesis(Assignments -> Settings -> Fitter/Physical Synthesis options), and I try to avoid these if I can. There are plenty of designs where they do wonderful things to close timing, but if they're not needed please turn them off. That's usually a good starting point as to where the bulk of compile time is being spent. When you say 30m-1hr with no changes and full incremental compile on, what are your partitions set to? Do you have physical synthesis turned on?

[Altera_Forum]

Also, if you have tight timing constraints, it will increase your fitter times. Sometimes you can dramatically reduce the fitter time by using pipelining, cut-paths, etc. I've seen where having too much combinational logic between registers will cause the fitter to work harder(more time) to try to make timing. If your only at 60% LE usage, try setting optimization to speed.

[Altera_Forum]

Yes, I do have physical synthesis turned on. Unfortunately the altera PCIe IP core (which I'm using in this design) will not meet timing when I turn it off. I have worked with an Altera FSE on this and we can't find any way around this. 

 I've tried all the normal things to get the compile times down (reducing timing constraints where possible, pipelining my portion of the design, setting the compiler to optimize for speed, etc)..  I appreciate the responses, but would be really interested to know what kind of compile times other users of the ArriaGX are getting...  Thanks, Frank

[Altera_Forum]

How much of your compile time is due to FSYN? There are messages the fitter puts out(in the .fit.rpt) that say exactly how long it takes and an estimate of how much it helped. Note that depending on your settings, the algorithms run twice, so you might see two batches of settings. I'm guessing this is a large culprit, and you can quickly see how much compile time you would save without this(i.e. if your design was like those that don't need this option turned on). 

You might be able to turn the FSYN effort down, or possibly turn some of the options off. Even if you then miss timing by a little bit, it should work in the lab.  The biggest impact is probably to put this core into a partition, possibly a logiclock region, and compile with FSYN turned on, possibly at the highest level. Then set it to post-fit(strict) so it is locked down(I assume you're not making changes to it). From there on out, run compiles with physical synthesis turned off.