Problems about DDR2!

[Altera_Forum]

Error: Too many output and bidirectional pins in I/O bank 3 assigned near VREF pin AB11 (VREFGROUP_B3_N1) on device EP3C120F780C7 -- no more than 9 output and bidirectional pins allowed near the VREF pin when voltage referenced pins are driving in, but there are potentially 10 pins driving out 

 It's the error report in the Quartus II. I use Band 3 to connect to the DDR2 SDRAM module, and other pins left in the bank to connect to a 1.8V SRAM. Who can tell me what the problem is? Thanks!!

[Altera_Forum]

It looks like Quartus already told you what the problem is, you have more than 9 outputs associated with VRef pin AB11 (9 being the limit). 

 Open the Pin Planner and click on "Show VREF Groups" on the toolbar. Make sure you have maximum 9 output/bidir pins in each VCCIO group for all voltage referenced I/Os - if you have more than 9, you can swap them with inputs (or leave unassigned).  For more information, read the cyclone iii handbook - i/o features (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51007.pdf), page 7-25.

[Altera_Forum]

I have already read the datasheet you said for several times, but I am confused. I only konw the meaning of the "Vref group", but what is the exact meaning of the "VCCIO group"? Does it mean different I/O pins are associated with different VCCIO?

[Altera_Forum]

VCCIO/GND pairs are distributed accross the chip to minimize the I/O switching noise. There is no hard delimited VCCIO groups within an I/O bank. 

 There is no information (as far as I know) about which I/O pins are close to each VCCIO pair. The closest information we have is the VRef groups, that's why I suggested you use that as a guideline for placing your I/Os.  Just try to keep 9 or less outputs/bidirs in each VRef group. You can try having more, but you will have to run the fitter repeatedly to see if Quartus accepts it. As a rule, make sure you lay out the schematic/PCB AFTER you have successfully placed your pins and ran the fitter with no errors.

[Altera_Forum]

In the Assignment editor you can use the "Output Enable Group" option to group bi-directional pins that are always in the same direction (e.g. dq and dqs lines of DDR). This can help with this error.

[Altera_Forum]

Hello, 

 the output enable group entry is important. When you use e. g. the Quartus DDR2 "High Performance Controller" reference design, this option is automaticly set from tcl script ddr2_pin_assignments.tcl together with IO standards.   But it could be, that your design flow is different from Altera predestinated way. Then you get the said errors, possibly wondering if your design would be operational at all.  Unfortunately, the output enable group option is neither mentioned anywhere in DDR2 controller user guides, nor in device handbooks where SSO constraints are discussed.  Only Quartus software handbook has an appropriate description:   --- Quote Start ---  For interfaces that use bidirectional VREF I/O pins, the VREF restriction must be met when the pins are driving in either direction. If a set of bidirectional signals are controlled by different output enables, the I/O Assignment Analysis command treats these as independent output enables. Use the output enable group logic option assignment to treat the set of bidirectional signals as a single output enable. This is important in the case of external memory interfaces. (A full page of examples follows)  --- Quote End ---    Regards, Frank