ArriaII GX and SDI MegaCore Function

[Altera_Forum]

HD-SDI's refclk frequencys are 148.5MHz and 148.35MHz. 

I am planning to swicth 148.5MHz and 148.35MHz before SDI MegaCore Function by RTL programming.  example) assign refclk=sw? refclk1 : refclk2;// refclk1=148.5MHz refclk2=148.35MHz refclk go to tx_serial_refclk and rx_serial_refclk of SDI MegaCore Function  But if I assign GXB refclk(BANK QL) to refclk1 and refclk2, compile error occurs. Probably I have to put GXB refclk(BANK QL) in tx_serial_refclk (rx_serial_refclk )directly. example design is gated clock(selected clock). But if I assign CLK input(CLK* pin of BANK 3,4,5,6,7,8) to refclk1 and refclk2, compile error does not occur. I think there is a problem of Signal Integrity with using CLK input(CLK* pin of BANK 3,4,5,6,7,8) . Please tell me how to use selectable GXB refclk(BANK QL). In SDI MegaCore Function,there is tx_serial_clk1(option). Can I use this to select 148.5MHz or 148.35MHz?

[Altera_Forum]

Hi, 

 As I understand it, the transceiver refclk need to be coming directly from the dedicated transceiver refclk input pin. The gated clock is not allowed.

[Altera_Forum]

By the way, to switch between two data rate, I think you would also need to enable the TX PLL switching in the IP core to allow dynamic reconfiguration for data rate switching.

[Altera_Forum]

--- Quote Start ---  By the way, to switch between two data rate, I think you would also need to enable the TX PLL switching in the IP core to allow dynamic reconfiguration for data rate switching.  --- Quote End ---    Thank you, nic_@-san,  To enable the TX PLL, Should I use tx_serial_refclk,tx_serial_refclk1 of SDI MegaCore Function? Is the item TX PLL select/reconfig in dynamic reconfiguration(AN588 page 30)? Please tell me switching method in detail.

[Altera_Forum]

The PLL input clock will need to come from a dedicated pin. You won't be able to select one of two unless the PLL supports this. 

 A quick look through the serial digital interface (sdi) megacore function user guide (https://www.google.com.ua/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cbsqfjaaahukewjshvugofvhahuevj4khwl4brg&url=https%3a%2f%2fwww.altera.com%2fen_us%2fpdfs%2fliterature%2fug%2fug_sdi.pdf&usg=afqjcney2c4muerg1n9m0-5whyhnsdwuig&bvm=bv.102829193,d.cww) tells me - on page 3-3:    --- Quote Start ---  Internal switching between two reference clock signals in the transmitter block. This feature is optional and only available for Arria II GZ, Stratix IV GX , and HardCopy IV devices.  --- Quote End ---     Your tittle suggests you're using ArriaII GX. So, you may struggle to do what you want to.  Cheers, Alex

[Altera_Forum]

If it's possible to modify the PCB design you might consider a programmable clock generator outside the FPGA. The clock generator would feed one reference clock to the FPGA but you can reprogram it to change the frequency. Silicon Labs makes some nice parts, but there are other options. 

 Another trick you could try is to select the clock you want, then route that out of the FPGA and loop it back externally to the single reference clock input pin to the SDI core. This would also require a PCB change, but a much simpler one.  A third option is to just not use the 148.35MHz clock, which is only required for video standards with frame rates like 60/1.001. The /1.001 frame rates are legacy broadcast stuff and most equipment that I know of will run just fine without that divisor. You might re-check your requirements and see if you really need to support those oddball standards.

[Altera_Forum]

--- Quote Start ---  If it's possible to modify the PCB design you might consider a programmable clock generator outside the FPGA. The clock generator would feed one reference clock to the FPGA but you can reprogram it to change the frequency. Silicon Labs makes some nice parts, but there are other options.  Another trick you could try is to select the clock you want, then route that out of the FPGA and loop it back externally to the single reference clock input pin to the SDI core. This would also require a PCB change, but a much simpler one.  A third option is to just not use the 148.35MHz clock, which is only required for video standards with frame rates like 60/1.001. The /1.001 frame rates are legacy broadcast stuff and most equipment that I know of will run just fine without that divisor. You might re-check your requirements and see if you really need to support those oddball standards.  --- Quote End ---     Thank you for your Advices. I'm answering about 3 of upper advice in the attachment.The part addition is difficult. My suggestion is to use a general clock in the attachment. It's also considered to abolish /1.001 clock rate.If there is a problem , please advise me.

[Altera_Forum]

--- Quote Start ---  Thank you for your Advices. I'm answering about 3 of upper advice in the attachment.The part addition is difficult. My suggestion is to use a general clock in the attachment. It's also considered to abolish /1.001 clock rate.If there is a problem , please advise me.  --- Quote End ---    When I use tow GXB refclks(148.5MHz and 148.35MHz) and select clock in FPGA,compile error occurs. Because GXB refclk does not connect XX_serial_refclk of SDI IP directly. So I put SDI dmmy CH and connect refclk to Dummy CH directly. Then compile error does not occur. By this way,I can use GXB refclks and select them in FPGA.  Please see attachment for details. If there is a problem, please tell me.