ArriaV FPP implemention

[Altera_Forum]

hi all , 

i want to configure the fpga through external CPU & CPLD,   all the FPGA configuration pins are connected to REGISTERS in the cpld. the cpu can asset -nCONFIG , read nSTATUS & CONV_DONE signals via registers in the cpld. the cpu writes the fpga configuration data to specific register in the cpld and the CPLD writes it to the FPGA. my question is: it takes to the cpu more than one clock to write valid configuration DATA into the CPLD data register. is it correct that i will geterate one pulse(one clk) on DCLK pin on evey valid cpu write data register?   wiil it be fine that delay is going to change (and not constant ) between pulses on DCLK signal you can see attached document   thanks, or shoshani

[Altera_Forum]

You're on the right track. 

 This document has details on how to write your own custom controller:  http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf  Altera also has the Parallel Flash Loader (PFL) megafunction  http://www.altera.com/literature/ug/ug_pfl.pdf‎  You could read that document for more info.  Cheers, Dave