Re: Asic Equivalent Logic of a Stratix 2 design

Altera_Forum · ‎11-30-2007

Hi,

How could I know the equivalent number of Asic Standard Cell of a Stratix 2 design:

250 Aluts

169 Logic register

2 PLL

Is it correct to say that 1 ALUT equals 4 logic gates and 1 logic register = 2 logic gates??

Thanks!!

Altera_Forum · ‎11-30-2007

Anything that small will be IO limited in a Standard Cell, so it probably doesn't matter. There is no 1:1 correlation though. An ALUT could be a large XOR gate, which would be a lot of gates, or it could be a 2 input AND gate. So it's really tough to correlate the two until you start porting your code to the ASIC library. What are you trying to target? (Not necessarily vendor, but what technology, etc.?)

Altera_Forum · ‎11-30-2007

Ahh...

The age old question of "gate' to FPGA resources.

First he easy answer - No, it is not correct to say "1 ALUT equals 4 logic gates and 1 logic register = 2 logic gates".

(an ALUT is upto an 8 input Boolean function)

(A Register is made up of much more then 2 logic gate, maybe as many as 10 -12)

But the real answer is much more challenging then that .

And every one you talk to will most likely give a different answer as well.

One itimized list I have heard used is to multiply the FPGA stated resources by 9 to 12 to get to ASIC gates. On average this is not a bad in the ball park guess.

Other info I have read on the subject might also say;

4 transistors = 1 gate (2 input NAND)

A memory bit (SRAM) consumes 6 transistors.

(You may have heard of a 6-T memory cell)

IBM counts all of the transistors (logic and memory) and divides by 4.

So….A 2S180 would look like this.

Logic gates 180k *12 (gates we claim in a LUT) = 2.16M

DSP gates = ~ 1M

(8mb memory *6) /4 = 12M

Clocks, test, length base buffer insertion, slew rate fixing

= 10% overhead of logic = .216M

So a 2S180 = 2.16 + 1 + 12 + .216 = 15.376 million gates.

Of course, in an ASIC they are 100% utilized

and in an FPGA or Structured AASIC you only use what you use.

So, if someone uses an Altera memory to gate ratio, it looks like a big part.

If the design is logic intensive, it looks pretty small.

I hope this helps.

Altera_Forum · ‎12-03-2007

Thanks for yours responses...

I found the detail of the resource usage:

Combinational ALUT usage by number of inputs

-- 7 input functions 1

-- 6 input functions 35

-- 5 input functions 38

-- 4 input functions 34

-- <=3 input functions 125

Combinational ALUTs by mode

-- normal mode 185

-- extended LUT mode 1

-- arithmetic mode 47

-- shared arithmetic mode 0

The ASIC technology could be 65 nm (Standart Cell)...

Altera_Forum · ‎12-03-2007

Note this has nothing directly to do with gates. A 6-input XOR gate uses more gates than a 6-input AND gate. Arithmetic mode(using the carry-chain) adds more gates. Control signals to the registers(clock enables, synchronous loads, etc.) adds more gates. You can get in the ballpark with this, but remember that's about it.

Altera_Forum · ‎11-06-2008

yup yup u r correct:) Also congrats to peter eastgate (http://www.pokerstars.com/wsop/novembernine/peter-eastgate/) who I believe also posts here, good job mate :)