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What's the max fanouts of the PLL's output clock?
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If you refer to the internal clock distribution, read about global clock nets in the respective device handbook. General, it won't be a problem to supply it to all lgic cells in your FPGA. If you mean the external clock output, read about the specification for the I/O standard of your choice.
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The PLL output goes through a global buffer, and the internal fanout of a global buffer is unlimited.
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