Asynchronous Set Registers - Cyclone III

[Altera_Forum]

I am examining an IP Core for use within a Cyclone III LS. It notes that it is necessary to have asynchronous set and resets on the registers implemented in the FPGA. I am pretty sure asynchronous resets are available in the Cyclone III, but are asynchronous sets? 

 Thanks!

[Altera_Forum]

The FPGA registers only have asynchronous resets, but the software can emulate an asynchronous set by using a not push back. 

 However, this means you can only have either an asynchrnous set or an asynchrnous reset in a register. You can't have them both on the same register.  You can't also have a register initialized to 0 with an asynchronous set or, vice-versa, a register initilized to 1 with an asynchronous reset.

[Altera_Forum]

Ah, so one or the other, but not both? 

 Hmm, since there's no work-around, I'll see if I can figure out why the IP Core needs these signals to be asynchronous.

[Altera_Forum]

Tr this: 

  process(set,reset,clk) begin if reset = '1' then data_out <= (others => '0'); elsif set = '1' then data_out <= (others => '1'); elsif rising_edge(clk) then data_out <= data_in; end if; end process;