Avalon MM Master BFM unusual Behaviour

[Altera_Forum]

Dear reader, 

 I try to simulate the behavior of my Avalon MM slave code. Avalon MM slave is part of my DUT which has a ROM and RAM memory connected. Avalon Master BFM is part of my test bench. here i try to verify the pipe-lined read transfer mode by reading data from ROM. With the same Avalon slave code verified all other(Burst write/read, only burst read, typical single write/read without burst mode) wirte/read transactions are Ok and are according to the Avalon MM specification  From the two attached images, in ram_pipelined_write_read_mode.gif you can see the read transactions i.e., the behaviour of READ, READDATA, READDATAVALID and WAITREQUEST are behaving as per the specification.   But in rom_pipelined_read_doubt.gif the behavior of read transaction is strange. What the problem here is Master BFM asserts READ request when WAITREQUEST is asserted (HIGH). As per the Altera Avalon MM specification the master should keep the ADDRESS and READ signal constant untill the WAITREQUEST is deasserted(LOW). But still the bus can read out the proper READDATA along with READDATAVALID. ROM read latency is 6 cycles. Would someone help me to clarify, why such difference in behaviour between the read transactions(READ/WAITREQUEST pairs) in ram_pipelined_write_read_mode.gif and rom_pipelined_read_doubt.gif  thanks in advance, Sanna