In using the Altera SPI core, I have a question regarding the SS_n select line.
In my old design, I was using some 'bit-bang' pots and the addressing scheme to individually select the pots was accomplished using an address decoder, and this worked fine.
I am now using some SPI interface pots (specifically the AD5290, 8 bit SPI interface) and I have my SPI core setup in the Master mode. I am still using the external circuitry to perform the selection of the individual pots (i.e. NOT the SS_n line) and I am wondering if this will work correctly with the SPI core’s operation.
When I look at the SCLK, the MOSI, and the CS select line, I see the following;
1) The CS line goes active low (control command issued to set lines)
2) Call the alt_avalon_spi_command
3) The correct data appears on the MOSI
4) The SCLK is present and in the correct timing location, and all 8 bits get clocked.
5) There is then a short pause
6) Now the MOSI line drops to zero (no data)
7) The SCLK now clock in the zero data
8) Return from the alt_avalon_spi_command call
9) The CS line goes high
I have no idea why the zero data is showing up on the MOSI line, and why it gets clocked into the device.
Must I use the SS_n line to control the addressing????
Thanks!
Fred
