Dual port Fifo with 400MHz

[Altera_Forum]

Hi, 

I never worked with FPGAs until now :confused:.   I need a dual port FIFO with the following specs: At the input side I want to gather blocks of data from a AD system with 400MHz clock rate, 14-28 bit wide (possibly also 42 or 56 bits wide).  At the output side I want to output the data to a USB microcontroller with a typical speed of 10MHz, 16 bit wide.  The FIFO buffer size should be about 20kByte.  Is this possible with an Altera FPGA and with which Family?

[Altera_Forum]

A high performance family, e.g. Stratix III can operate internal RAM at 400 MHz, a medium performance series (Cyclone III) could manage the data throughput by splitting the data rate in two memory blocks operating at 200 MHz. It should be basically possible with both.

[Altera_Forum]

Is there a simple demo application available somewhere, where I can see how to implement a FIFO in a Cyclone III?

[Altera_Forum]

The Quartus FIFO MegaFunction (scfifo) has all necessary options, I think.

[Altera_Forum]

:rolleyes: Please do not laugh at me, but I would very much like to get a FPGA in a QFP housing for the beginning (avoiding BGA - this would simplify the PCB soldering considerably). 

 I looked through the Cyclone III documentation and found the EP3C40Q240C8 in the P240 housing with 128 IOs and 126 M9K memory blocks (=about 126kByte, well enough for me).   Summing up the pins, I reach 72 for the standard app (28bit * 2 for LVDS on the input side= 56, and 16 bit on the output side (no LVDS)), so I have 56 free pins for control and clock, this definitely should be enough.   Is this calculation approximately ok and this Chip would be ok for me? (unfortunately P240 housing only available in speed grade C8 - but this specifies 238 MHz for the memory, which is I hope sufficiently above my needed 200MHz).   :confused: (I feel especially unsure concerning your remark of the necessary bus splitting: Is it possible to do this in the FPGA array, or is it necessary feed the 28 input bits two differents LVDS inputs each - in this case of course I could bury my QFP dreaming, as then I would additional 56 pins alone for the bus splitting).

[Altera_Forum]

Sounds like ADS5474. 

 I don't intend to work out the design details, but it's most likely necessary to perform the 1:2 demultiplex directly at the LVDS  inputs with an altddio_in function, using DRY as aquisition clock. If I understand right, Cyclone III C8 isn't able to provide a  400 MHz output clock. However, to utilize the ADC performance specification, a low jitter external clock should be used anyway.  The clock jitter of a FPGA PLL output (with FPGA families that support 400 MHz clock output) would be unsuitably high anyway.  Considering the ADC prices, a higher performance FPGA should still fit the design, I think. But as far as I see, it can work with Cyclone III.