m9k memory blocks in cyclone3

[Altera_Forum]

hi 

i created ram with one read and one write port using megawizard function, while reading that memory 3 clock cycles delay is coming, can any one help me,

[Altera_Forum]

I think there is an option to register inputs and/or outputs so the clocks are needed for the registers. In effect there may be a 2 stage pipeline in the ram.

[Altera_Forum]

hi..thanks for ur reply... 

i removed that output registering option... still i am getting one clock cycle delay while reading the data from that memory

[Altera_Forum]

There is a 1 clock cycle minimum delay to read data from the memory. Address is latched on 1st clock, data available on second. 

 Jake

[Altera_Forum]

--- Quote Start ---  hi..thanks for ur reply... i removed that output registering option... still i am getting one clock cycle delay while reading the data from that memory  --- Quote End ---    If you are registering the address and then clocking the ram, then the clock of the registerwould be in the path.   Suggest a close look at the waveforms for read in the manual to see if you may have an unneeded register. It is not easy to analyze, but to me, the address is latched on the first half of the clock and the data becomes available during the second half making it available at the next clock.  Please let me know your conclusion, because I am not positive.