Avalon-ST spec contradiction.

[Altera_Forum]

Hello, 

 In "Avalon Interface Specifications" rev 15.1 2015.12.10 in table 5-1 one can see in a row "ready":   --- Quote Start ---  The source may only assert valid and transfer data during ready cycles.  --- Quote End ---   It seems that it is forbidden to assert valid when ready=0.  On the other hand in section 5.9 (paragraph 3) it is written:   --- Quote Start ---  In this mode, the source does not receive the sink’s ready signal before it begins sending valid data.  --- Quote End ---   So we have to assert valid (if we have data to send) before ready is 1. figure 5-7 (valid = 1, ready = 0 at the same time) confirms second quote.  Do we have right to assert valid even if we have ready = 0?  Thanks

[Altera_Forum]

My interpretation: pay particular attention to the word "and" within Table 5-1. 

   --- Quote Start ---   The source may only (assert valid and transfer data) during ready cycles.   --- Quote End ---    i.e. asserting valid is part of the act of transferring data, and that transfer only happens during a ready cycle. If you assert valid, and change data bits, while ready is not asserted - then I believe this is a violation of the protocol specification, for example.  Anyway, the answer to your question is yes, you can assert valid while ready=0.