BLVDS in Cyclone IV E

[Altera_Forum]

Hello, 

 i did not find some good note how to implement bi-dir BUS LVDS on Cyclone IV E. My current settings still returns error.   I have one differential signal on fpga which should be used as blvds to half duplex communication between a few cards. There is a note in the manual BLVDS can be used as bidirectional bus to half-duplex communication. The second note which I found says that differential signals have open-drain option disabled. It does not make sense to me. How can I enable open-drain for BLVDS? Because when I use bi-dir blvds quartus returns this error message:  Error (169008): Can't turn on open-drain option for differential I/O pin fe_reset_n_p  When I use ALTIOBUFF and when differential mode is selected then open-drain cannot be used.  Can Cyclone IV E use bi-dir blvds for half-duplex communication?  Thank you for help, vkle

[Altera_Forum]

Hi vkle, 

 There is a document on this. Does this document help?  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an522.pdf

[Altera_Forum]

Hi, 

 unfortunately not. When I choose BLVDS and ALTIOBUF then it returns Error (169008): Can't turn on open-drain option for differential I/O pin fe_reset_n_p. This note does help not with this issue.  BR, vkle

[Altera_Forum]

Open drain makes no sense at all for BLVDS. Why do you want to enable it?

[Altera_Forum]

Beucase it would be nice to have just one signal for communication. I agree is sounds strange. But there is an sentence in documentation BLVS can handle half duplex communication on one diff signal. This app. note: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an522.pdf 

 There is described setup tx and rx on one diff signal.

[Altera_Forum]

Hi, perhaps u can refer to this link for a workaround  

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12132011_100.tablet.html

[Altera_Forum]

Hi, 

 it ends by this error:  Error (176718): Pin fe_blvds0_n uses pseudo-differential output node blvds_driver:i_fe_blvds_reset_n|blvds_driver_iobuf_bidir_l3q:blvds_driver_iobuf_bidir_l3q_component|pseudo_diffa. However, these pins also have an I/O standard LVDS that cannot be supported by the pseudo-differential output node.  vkle