BRAM implementation in Altera Quartus

[Altera_Forum]

Does anyone here know how to implement BRAM in Altera Quartus?? The inferred BRAM in my design isn't working in my synthesizer and i get logic instead of BRAM. Thats why compilation of my design failed 

 Regards, Bruno Kasimin

[Altera_Forum]

Which FPGA are you using?

[Altera_Forum]

Cyclone EP1C12F324C8

[Altera_Forum]

I don't know exactly why you want to use "BRAM", maybe you are starting from a Xilinx project and trying to convert it to Altera? 

Anyway, I believe that you may instantiate an Altsyncram block and adapt it to your needs. It is a Megafunction available free of charge in Quartus.

[Altera_Forum]

Actually i am implementing a soft-core processor a.k.a zpu microcontroller which i have downloaded from www.opencores.org. What i'm trying to do is implementing simplest version of zpu uses BRAM on Altera Cyclone. If i were successfull then i can see the 'helloworld' on the screen of hyperterminal..The 'helloworld' in the bram is the input of my zpu processor. And how can i use altsyncram??i just found that in megafunction, but i didnt know how to use it cause it has a lot of inputs a and the inputs have strange names, which make complicated for me to use.Do you know where i can get the documentation on it?

[Altera_Forum]

Yes, it is very simple. 

On the Quartus choose Help --> Megafunctions/LPM --> Memory Compiler Megafunctions

[Altera_Forum]

You might be able to modify the HDL to enable synthesis to infer the RAM. See "Inferring Memory Functions from HDL Code" in the Quartus handbook, Volume 1, Section II, Chapter 6, "Recommended HDL Coding Styles". If you want to use features of the RAM block that synthesis does not support for inferred RAM, then you need to instantiate an altsyncram MegaWizard variation as OrchestraDirector suggested.

[Altera_Forum]

at one stage i need to use the files in the format of .hex or .mif as memory content. But the helloworld data only available in BRAM-file or bin-file in the files i've downloaded.do know how to convert it into .hex or .mif file? Or can you help me to convert the file in the attachment into .hex and .mif file?

[Altera_Forum]

I would open hello.bram Excel as a text file with the double quotes used as delimiters and the data column formatted as text. It should be easy enough to edit in Excel so that you can save it to a text file in the .mif format. To get an example of the .mif format, create a dummy .mif file in Quartus with 32-bit data.

[Altera_Forum]

I've just copied all the data from excel and i put them in my new .mif file format.Because i have 3054 data, i formatted the new .mif file with number of words 4096.That means starting from 3054 to 4096 are all 0. Am i correct??

[Altera_Forum]

Typically the not used bytes are 'FF' in the mif file, but they are dont-care values if you don't read it from the altsyncram block. So also '00' is an acceptable value if not used.

[Altera_Forum]

Now i have data stored in .mif file as memory content of altsyncram0 block. In my files in working directory, there is alsyncram0.vhd which is automatically generated by the creation of block. Is it fixed or i can edit it? i need to put in behaviour of the block. you can see my attachment of helloworld.vhd which contains RAM data and its behaviour.

[Altera_Forum]

You may edit the vhd file if you know exactly which parameters of the Altsyncram block are affected by your changes. You can use this vhd file as any other VHDL source file in your top level design. 

But you can also recall the Megawizard to make changes on the block or you can edit the mif file if you just need to change the content of the ROM.

[Altera_Forum]

This is the generated VHDL file of the asyncram block: 

  ENTITY altsyncram0 IS  PORT  (  address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);  address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);  clock : IN STD_LOGIC ;  data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);  data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);  wren_a : IN STD_LOGIC := '1';  wren_b : IN STD_LOGIC := '1';  q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);  q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)  ); END altsyncram0;   ARCHITECTURE SYN OF altsyncram0 IS   SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);  SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);     COMPONENT altsyncram  GENERIC (  address_aclr_a : STRING;  address_aclr_b : STRING;  address_reg_b : STRING;  indata_aclr_a : STRING;  indata_aclr_b : STRING;  indata_reg_b : STRING;  init_file : STRING;  intended_device_family : STRING;  lpm_type : STRING;  numwords_a : NATURAL;  numwords_b : NATURAL;  operation_mode : STRING;  outdata_aclr_a : STRING;  outdata_aclr_b : STRING;  outdata_reg_a : STRING;  outdata_reg_b : STRING;  power_up_uninitialized : STRING;  read_during_write_mode_mixed_ports : STRING;  widthad_a : NATURAL;  widthad_b : NATURAL;  width_a : NATURAL;  width_b : NATURAL;  width_byteena_a : NATURAL;  width_byteena_b : NATURAL;  wrcontrol_aclr_a : STRING;  wrcontrol_aclr_b : STRING;  wrcontrol_wraddress_reg_b : STRING  );  PORT (  wren_a : IN STD_LOGIC ;  clock0 : IN STD_LOGIC ;  wren_b : IN STD_LOGIC ;  address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);  address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);  q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);  q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);  data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);  data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)  );  END COMPONENT;  BEGIN  q_a <= sub_wire0(31 DOWNTO 0);  q_b <= sub_wire1(31 DOWNTO 0);   altsyncram_component : altsyncram  GENERIC MAP (  address_aclr_a => "NONE",  address_aclr_b => "NONE",  address_reg_b => "CLOCK0",  indata_aclr_a => "NONE",  indata_aclr_b => "NONE",  indata_reg_b => "CLOCK0",  init_file => "F:/hello.mif",  intended_device_family => "Cyclone",  lpm_type => "altsyncram",  numwords_a => 4096,  numwords_b => 4096,  operation_mode => "BIDIR_DUAL_PORT",  outdata_aclr_a => "NONE",  outdata_aclr_b => "NONE",  outdata_reg_a => "CLOCK0",  outdata_reg_b => "CLOCK0",  power_up_uninitialized => "FALSE",  read_during_write_mode_mixed_ports => "DONT_CARE",  widthad_a => 12,  widthad_b => 12,  width_a => 32,  width_b => 32,  width_byteena_a => 1,  width_byteena_b => 1,  wrcontrol_aclr_a => "NONE",  wrcontrol_aclr_b => "NONE",  wrcontrol_wraddress_reg_b => "CLOCK0"  )  PORT MAP (  wren_a => wren_a,  clock0 => clock,  wren_b => wren_b,  address_a => address_a,  address_b => address_b,  data_a => data_a,  data_b => data_b,  q_a => sub_wire0,  q_b => sub_wire1  );  END SYN;  First of all, i have created the behaviour of the block:  process (clk) begin  if (clk'event and clk = '1') then  if (wren_a = '1') and (wren_b = '1') and (address_a=address) and (data_a/=data_b) then  report "write collision" severity failure;  end if;    if (wren_a = '1') then  ram(to_integer(unsigned(address_a))) := data_a;  q_a <= data_a;  else  q_a <= ram(to_integer(unsigned(address_a)));  end if;   if (wren_a = '1') then  ram(to_integer(unsigned(address_b))) := data_b;  q_b <= data_b;  else  q_b <= ram(to_integer(unsigned(address_b)));  end if;  end if;  end process;  Now i'm having difficulty on where i should put this code in generated vhdl from asyncram. anyone has idea?

[Altera_Forum]

I suggest you to create a top-level bdf file in which you create a schematic with connections between block symbols. 

Every vhdl file that you have created can be transformed into a block symbol by opening the vhdl file and using the menu File --> Create/Update --> Create symbol files for current file  In the top level bdf file you can insert each block symbol that you have created in this way. The connections between the blocks can be created using wires and busses. In this way you can connect your altsyncram block to the surrounding blocks by simple wires, without having to modify its automatically generated code. I hope this helps.

[Altera_Forum]

i understand what you meant but the outputs of the asyncram block are actually are also output in my created vhdl files. So what i think is, my vhdl should be internal,i mean created vhdl must be somewhere inside the the altsyncram block and is not external as you mentioned before.I'm still confused about this.Further hints???

[Altera_Forum]

The altsyncram block is the source of your data (since you have used it in ROM mode) and can be instantiated directly by placing the block symbol into the top-level schematic. The block symbol will automatically recall the vhdl file which has been generated by Quartus II. So, if you use the schematic approach, you don't have to care about the vhdl file because it will be already "embedded" into the block symbol.

[Altera_Forum]

I've tought about something. Is there any process already made in asyncram block i created?

[Altera_Forum]

The altsyncram block by itself does not include any process. The process that you have created (that you have called "the behaviour") is to be implemented as a stand-alone controller block outside the altsyncram block. 

So the altsyncram is a simple data container and your external controller block decides when and how to read data from the memory. I hope that it is clear enough.

[Altera_Forum]

Is it possible to locate BRAMs in the Chip Planner?