Hi, I am new to design FPGA.I have a PAC board with it's BSP. However, I still want to customize my own BSP. I follow the tutorial about how to make customized BSP.
Here is my step: Have a copied of a10_ref BSP. Modified device.tcl device to 10AX115N3F40E2SG. (refer to PAC device.tcl) In board.qsys, acl_ddr4_a10.qsys, acl_ddr4_a10_core.qsys, Sync All System Infos -> Generate HDL -> Finish Modified pin assignment. (refer to PAC pin assignment, like PCIE, memory, refclk ...) In acl_ddr4_a10_core.qsys ddr4a EMIF IP General set memory clock frequency to 1066. ( I set to this because my board memory is DDR4 2133, and a10_ref use DDR4 2400) use recommanded PLL reference clock frequency Mem Timing set Speed bin to -2133 Sync All System Infos -> Generate HDL -> Finish In board.qsys kernel_clk_gen set REF_CLK_RATE to 100 config_clk set Explicit clock rate to 100000000 Sync All System Infos -> Generate HDL -> Finish In top.v reg config_clk; // because in a10_ref, it need 50MHz config_clk, and I only have 100MHz kernel_pll_refclk always@(posedge kernel_pll_refclk or negedge perstl0_n) begin if (!perstl0_n) config_clk <= 0; else config_clk <= ~config_clk; endHowever, the system will crash when I try to send data to external memory DDR4. I have upload the log file. It would be very helpful, if someone can tell me what's wrong. and I also have some question about EMIF IP. what should I set in General memory clock frequency? what should I set in General PLL reference clock frequency? what is Speed bin in Mem Timing? I know I have to assign a pin to pll_ref_clk, is this pin clock should match PLL reference clock frequency? and in a10_ref emif ip, it set memory clock frequency to 1200, and PLL reference clock frequency to 300MHz, I am not sure what clock it provide to pll_ref_clk, but in top.sdc file I see an assignment "create_clock -period 150MHz [get_ports pll_ref_clk]" So I guess it assign 150MHz clock when it set PLL reference clock frequency to 300MHz. Why it work?