BUS TAP in quartus prime lite

[Sayali]

In custom designed PCB board with Intel MAX V CPLD, In order to feed 9 down to 0 counter output to one of the inputs of NOR GATE, i am not finding direct bus tap option available in Quartus prime 23.1 std lite edition. Below I am attaching the reference image for xilinx CPLD where bus tap is used at the counter output and Intel CPLD where I am using 12 input NOR gate in place of bus tap. 

please suggest the possible solution where I can do replica of below Xilinx CPLD image for Intel MAX V 5M160ZE64 CPLD. 

[FvM]

Hi,
as far as I'm aware of, a bus tap is connecting a single bus bit. The drawing however suggests a logic operation, e.g. or_reduce(). Does Xilinx provide a feature to assign a logic operation to a bus tap?

Or reduce is available as operator in VHDL or Verilog, you can make a block schematic symbol performing this function, but why?
Explicitely connecting bus bits to or gate doesn't seem too complicated.

[RichardTanSY_Altera]

Unfortunately, Quartus Prime does not provide a graphical "bus tap" feature similar to what Xilinx offers.

However, as suggested by FvM, you might be able to replicate the same functionality by implementing the logic manually.

Regards,

Richard Tan

[Sayali]

Hi,

Basically, In Xilinx I have three counters having same source code whose output that is X[9] count  (last count)  goes to one of the inputs of NOR Gate through bus tap and further to CLK of counter and counter works respectively for next reset signal as shown in Xilinx_V1 image attached. Also, the same count X[9] of counter goes to further combinational logic.

So, while I replicate this same in Quartus, I cannot use three counters with same source code as quartus gives error for Q1[9], if I use it for all three counters. So, for this currently I have used three counters having output Q1[9], Q2[9], Q3[9] with three different source codes namely counter1, counter2, counter3. I have attached image named Intel for reference.

My question is:  1. Will Q1[9] interpret 9th count of counter1 and feed it back to one of the input of NOR Gate correctly?

                              2. Is there any way where I can use counter with same source code for three times as used in Xilinx ?

Please suggest the possible solution to this.

[RichardTanSY_Altera]

What is the error message that Quartus is showing?
I’m not quite sure why Counter 1, 2, and 3 have different source codes. Aren’t they supposed to have the same functionality, just with different entity names? By the way, the picture is a bit blurry, so it’s hard to make out the details. Perhaps you could run the project using HDL code instead of schematic design.
Alternatively, with the verilog file e.g. counter.v verilog file, you can right-click the file for drop down option, click Create Symbol Files from Current Files to generate the symbol files. Now you can insert the counter block in your schematic. However, we still recommend users to use HDL instead using schematic. 

Also, does Xilinx provide a way to generate Verilog code from a schematic? If so, perhaps you could try running that code in Quartus?

Please note that we are specializes in the Quartus tool and we are unable to assist with any inquiries or issues related to Vivado.

Regards,
Richard Tan 

[RichardTanSY_Altera]

Any update on this?

Regards,

Richard Tan

[Sayali]

Thank you for your support. 

I have used counters with different entity names having same functionality as suggested.

Also, issue got solved using HDL file (.vhd) converted using .bdf file. 

[RichardTanSY_Altera]

I'm pleased to know that your issue has been resolved.

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan