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Hello, I am working with an Altera FPGA (Cyclone IV E) for the first time ever and I am starting to draw the schematic. There is one question I can't figure out about the IO Bank voltages.
I would like all of my IO Bank power supplies to be 3.3V. But the Cyclone IV configuration datasheet says that the TMS and TDI JTAG pins must be pulled up to 2.5V and it says the MSEL pins should be pulled up to 2.5V (or GND). My device is a EP4CE15E22. The JTAG pins are in IO Bank 1 and the MSEL pins are IO Bank 6. Can I use 3.3V power supplies for Bank 1 and 6 even though there are 2.5V signals on the JTAG and MSEL pins? (My configuration device is a EPCS4 which is 3.3V). Thank you for any help.Enlace copiado
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Yes, these are special IO's so even though they are in specific banks, do as the handbook describes.
I don't know what the internal structure of these specific IO's are, but they may but even if they are connected to the 3.3V bank IO, a 2.5 V input level is a valid high for a 3.3 V input. Pete- Marcar como nuevo
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Thank you for the answer.
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Ok now I have another question, because I'm curious...
What if I want to use an IO Bank voltage of 1.2, 1.5, or 1.8V on IO Bank 1 or 6. Then do I still follow the design handbook and pull up JTAG and MSEL pins to 2.5V?- Marcar como nuevo
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Yes. These are dedicated pins and must be treated so.

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