Best place for termination resistor

[Altera_Forum]

I am connecting a Micrel Gig-E PHY to a Cyclone III FPGA. Most of it is fairly straightforward - and I've got all GMII interface routed cleanly. 

 The only trick is the TXCLK/GTXCLK pin. It's a shared I/O pin on the PHY. In MII mode (10/100) the PHY transmits a 2.5MHz or 25MHz clock back to the FPGA. In GMII mode (1000), the FPGA transmits a 125MHz clock to the PHY.   To simplify matters, I've allocated two pins for the clock - one for the 125MHz output clock (GTXCLK), and a dedicated clock-in pin for the MII clocks (TXCLK). In GMII mode, I drive GTXCLK, and in MII mode, I tri-state it. I'm using the link activity indicator for 1000 mode to do the switching, under the assumption that the indicator will only be valid when the PHY is gigabit mode.   The dedicated clock-in always sees a clock, but in GMII mode, I can ignore it. This should allow the MAC core to think it has separate I/O lines.  The question is where to place the source terminating resistor. I know the best place would be right next to the output pin, but the trace runs under the FPGA. Right now, the resistor is right past the dedicated clock input pin, as it leaves the FPGA to the PHY. The clock line actually runs through the dedicated clock-in pad.  Is that going to be a problem? The only alternative is to drop to the bottom layer, pass through the resistor, and then pop back up to the top layer. There is way too much congestion to go around.  I know it sounds a bit anal, but I can't afford too many respins. I'm trying to get the "first" board as perfect as possible.  Thanks!

[Altera_Forum]

I think, FPGA internal series termination should be sufficient normally.

[Altera_Forum]

Is there a reason why you can't use one FPGA pin for both purposes? The Cyclone III Dev. board has a tripple-speed ethernet mac on it, and seems to use one pin?

[Altera_Forum]

I hadn't considered it, but the GTX clock out is on a local clock pin (DPCLK0), so theoretically it could be used as an input when in MII mode. It was a somewhat serendipitous route, as I didn't intentionally route the net there (I was trying to avoid vref pins, though) 

 If you configure those pins as bidirs, can you still route an input on the pin to the local clock net?   I had routed the signal to a normal I/O pin, and a dedicated clock-input pin, since I figured the MAC core clock would be a high fan-out net that would probably cross quadrants. At worst, I could try it. The wire is already there, but it really should hurt anything to have the dedicated clock-in pin "listening" - since it will be high-impedance.