CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Is there any functionality that will allow me to use net names (maybe not the right word) of signals on block pins for connections between blocks instead of running wires with the mouse which can get pretty messy and time consuming to wire.
--- Quote Start --- and you've stumbled upon one of the many reasons to use HDL instead of schematics :) --- Quote End --- I knew someone would say that:) I cant seem to find where i can use a net name on a pin though
You have to draw a net out from the block's pin and then right-click properties(or double-click) and name it. So you'll see a named wire extending from the pin.
