Blown ADC?

[Altera_Forum]

I'm currently designing an audio analysis system on a DE0-Nano board, I'd previously tested the ADC section of the design and all was working perfectly. 

 However now that it's come to final testing, something didn't seem quite right, I went back to test the ADC and am currently getting a really weird output. I've attached a couple of examples of the output i'm getting on SignalTap, I'm not sure if it's a fault in my code, or the actual chip is bust. Any ideas?

[Altera_Forum]

A lot of those signal jumps seem to be powers of 2, so you could have a timing problem. 

IIRC DE0-Nano has an ADC with spi interface: if spi has poor timing, it could sample twice the same serial bit and skip the next one, and this would lead to something like that. Does spi data from adc change on the right clock edge? Another common problem could be you are exceeding adc max conversion rate, then it returns you partial converted data. This is more probable if you are cyclicing on multiple adc inputs and you don't wait the required input selection delay.

[Altera_Forum]

I wouldn't say your ADC has blown. 

Looking at your ADC1 screenshot, it sounds like: 1) You are using a 12-bit ADC 2) When your signal amplitude goes down to zero, your data acquisition logic seems to interpret the ADC output code differently from what you are expecting. Does the SignalTap bus display format match the ADC output coding (signed/unsigned, binary or 2's complement etc...) ?

[Altera_Forum]

Thanks for the help guys. 

 Cris, it looks like you were right with the timing issue idea, I didn't have the data acquisition synchronised well enough and it was throwing everything out. I've since rewritten the entire module, and it's working much better than it was. I'm getting odd spikes at certain points within the waveform though, example attached.

[Altera_Forum]

This is again a timing issue. 

From the graph it's quite clear you are getting those spikes whenever the msb changes. For example when data crosses the half scale value 512, namely digital value changes from 01111111b to 10000000b, you read 11111111b, as if you get it when only the first bit has changed. Similarly, on the falling slope, you read 00000000b when it makes the opposite transition. If your ADC is kind of a SAR, this happens because you are failing to wait the required conversion time before reading the result.

[Altera_Forum]

Bingo. 

 Thanks for that mate, I've realised where it was going wrong now. I'd assigned my output to the register that was being used to convert from serial to parallel, and as such it was reading a parallel value out every time a bit changed. All sorted now though, it outputs the value after the LSB. Attached is a nice clean(ish) ADC output :)  Dave