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Altera_Forum
Honored Contributor I
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Boot loader, Cyclone 3 reconfiguration, in-circuit EPCS update

I developed the device based on Cyclone 3 with its config programmed into EPCS16 using active serial mode. 

To upgrade configuration external device and external software (e.g. byteblaster/usb blaster + Quartus II) are needed. 

I was asked if it is possible to design in the way that EPCS image is updated "in-circuit" (by the devices located on the board). 

In my design NCONFIG, CONF_DONE and NCE are going to AS config connector only, and NSTATUS goes nowhere. 

 

I did brief research on how Cyclone configures, but still do not have answer to this question. 

In my understanding it may be that EPCS is having several sections, first section with boot loader which configures FPGA providing r/w access interface to connected EPCS chip, the second section is "user configuration" (the main config used for device operation). When boot loader loads, and then can not load "user config", it keeps in boot loader mode accepting update of the EPCS device. This is needed in case user image is corrupt for some reason (e.g. bad update attempt). 

 

Is there any way to achieve this goal, given that those control signals are not fed back to FPGA? 

Or maybe I still miss something and it should be done differently? 

Thank you.
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Altera_Forum
Honored Contributor I
68 Views

Suggest to review the "Remote System Upgrade" chapter in Cyclone III handbook which is describing all the features you are looking for. There's also a "Remote Update IP Core User Guide" an "ASMI Parallel Megafunction User Guide" and an AN521 reference design.

Altera_Forum
Honored Contributor I
68 Views

Thank you very much for reply. 

 

 

Excuse me for ignorance, while I more or less have an idea how it works, I still have issues integrating all my knowledge into the design, and I can not find implementation examples. Most of documents describe process, but none has HDL code. 

 

 

What is cycloneiii_rublock megawizard refers to? 

 

 

So let me explain how I see it. I do not use Qsys or Nios or whatever, there will be pure "user logic" in there. 

 

 

On power on FPGA will configure with image located at address 0 (factory image). If I want to reconfigure from this configuration, I should include ALTREMOTE_UPDATE megafunction into the design. 

 

 

If I want to configure to factory image, I do not need "add support for writing configuration parameters", when I toggle "reconfig" line when "busy" is inactive, FPGA will go to factory image automatically. 

 

 

However if I want to configure to another image than default, I need "add support for writing configuration parameters" to be able to write address of the image to reconfigure to. 

 

 

Now about driving ALTREMOTE_UPDATE. As I understood it runs as independent circuit after configuration completes, thus I just design circuits which support the operation of ALTREMOTE_UPDATE basing on some external events. 

Guide states that there's internal OSC to connect "clock" to, but I can not find how to do it. I have only 18 MHz external clock, I can use PLL to double/triple its speed, but I am not sure what will it change. (what does this clock affect - only speed of controller, but not speed of following reconfiguration?). 

 

 

Guide also says that circuit requires reset, while on power up I can source proper reset signal (from external system), after reconfiguration I hardly can do it. 

Next, how ALTREMOTE_UPDATE knows which storage device is out there? From the project's "device/pin options"? 

 

And the last. How do I perform operations on EPCS device contents - also through ALTREMOTE_UPDATE? Where're erase, write and read operations? I can not find them in the guide...
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