Booting Cyclone 4 with STM32F407

[Altera_Forum]

Hello! 

 Iam so sorry but i didnt find any solution or whitepaper with circuit diagram where they are booting FPGA with ARM CPU. Does anyone know anything about this option? Is able to use classic SPI? Why altera does not provide any flowchart?  Thanks for repply

[Altera_Forum]

--- Quote Start ---   Iam so sorry but i didnt find any solution or whitepaper with circuit diagram where they are booting FPGA with ARM CPU. Does anyone know anything about this option? Is able to use classic SPI? Why altera does not provide any flowchart?   --- Quote End ---   Altera does provide details, but you probably looked for the wrong terms.  Altera FPGAs can be programmed by an external processor using 1-bit Passive Serial mode (sort of like SPI) or a multi-bit mode called Fast Passive Parallel.  I've implemented external configuration using a CPLD as a programming master, eg. read fpga_configuration.pdf on this page  https://www.ovro.caltech.edu/~dwh/carma_board/ https://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf  But I've also programmed FPGAs using FTDIs USB-to-Serial devices too, so I know you can get away with a simpler interface, eg., program the device using a serial interface, and then check the status signals to confirm you succeeded.  Cheers, Dave

[Altera_Forum]

Device configuration is covered in this section of the handbook: http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf 

 You're looking for Jam STAPL. Connect ARM GPIO's to the JTAG pins and port the source code for the player.  http://www.altera.com/support/devices/tools/jam/tls-jam.html

[Altera_Forum]

Could you please check the circuit below if is correct?https://www.alteraforum.com/forum/attachment.php?attachmentid=9607

[Altera_Forum]

--- Quote Start ---  Could you please check the circuit below if is correct?  --- Quote End ---    Since you cannot guarantee the state of the nCONFIG pin when the ST micro boots, you should have a pull-down, so that the FPGA is disabled until the micro enables it.  CONF_DONE and nSTATUS should have external pull-ups (or you can enable pull-ups on your micro pins).  You should have a source termination on your DCLK signal (back at the micro pin).  You need to double-check that the FPGA configuration pin voltages are compatible with your microcontroller (if they are all 3.3V, then they will be fine).  Make sure your design also includes a breakout of the FPGA JTAG signals to a standard 10-pin header. It will make debugging of your design simpler :)  Cheers, Dave

[Altera_Forum]

Many thanks for advices!