Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19496 Discussions

Booting from Onchip RAM


Hello everyone,

I am struggling with booting from on-chip RAM.

I am using Quartus 18.0 to work with Cyclone V FPGAs. I have done some tutorials like the AN458 and read some necessary sections of the recommended Reference Manuals and Handbooks.

I have implemented a small Hardware with two NIOS II.

The first NIOS (I call it Boot Copier NIOS):

- Has access to the EPCQ.

- Has an internal on-chip RAM for its application.

- Has a MM-Pipeline-Bridge to a separate dual ported RAM of the second NIOS.


The second NIOS (I call it DUMMY NIOS):

- Has access to the dual ported RAM which the Boot copier NIOS can access too.


The dual ported solution is realized with a separate MM-Interface for every NIOS to ensure an interference free access to the memory. After debugging it shall be replaced with a “one-ported” on-chip RAM and a Mutex concept.

If I am following the instructions from AN458, I can implement a small Boot copier on the EPCQ directly. The EPCQ copies the application of the Boot Copier NIOS directly to its on-chip RAM and the Boot Copier NIOS starts its application. This first step works well.

Now I want to have the application of the DUMMY NIOS also on the Flash, copy it actively with the Boot copier NIOS to the shared on-chip RAM and start the DUMMY NIOS.

For this problem I have checked the Boot Records which are also explained in the Tutorials. I also have checked the “generate mem init”, which Eclipse offers. Also, I have executed the elf2hex command and checked the content of the on-chip RAM during debugging. The result was that the content of the on-chip RAM, the “generate mem init” and the elf2hex have basically the same content. With the small difference that the memory initialization generates a bigger .hex because it has to initialize the whole memory and not only the application code. The application data in the boot record are looking different to the data on the on-chip RAM. Maybe there is a compression done during the Boot Record generation which generates a .flash file.

I decided to go for the “easier” way and flash the elf2hex generated .hex file to the EPCQ via the Quartus “Convert Programming Files” option. The Boot Copier NIOS boots from EPCQ (working) and writes (memcpy) the elf2hex generated .hex file of the DUMMY NIOS to the on-chip RAM which they are sharing. Afterwards, the Boot Copier NIOS releases the DUMMY NIOS from the soft reset and …nothing happens.

I have checked that the content is written from the Boot Copier NIOS to the shared on-chip RAM is identical with the content which would be there if the memory is initialized via “mem init generate” .hex”.

Now I seem to be at a dead end and need some support. Maybe I have some failure in the method, maybe with this way of booting the RAM content needs to be different to the RAM content which is generated via a “mem init generate”. Maybe I have messed something up with Reset and Exception Vector.

Why have I decided to go with that concept? This is just a small example project. If this works, it will be implemented with 4-8 NIOS II and an Update concept. For me this is a suitable way to go for more complex designs.

I would really like to hear suggestions of possible failures I have done in concept, method or implementation.

Thanks for your answer

0 Kudos
3 Replies

Hi @IMS,

Thank you for posting in Intel community forum, hope this message find you well and apologies for the delayed in response.
Clarification if I may, situation here is that we have a set of different NIOS with different flash, and you are trying to copy the application of both NIOS into the shared on-chip RAM to run it yes?
And only one of the NIOS application are successfully working?
If that is the case I would recommend the following tutorial here, as it would be a very good starting point for a multiple processor system.

Warm regards.


Hi @IMS,

Hope this message find you well and good day, unfortunately as we do not receive any response from you to the previous clarification and tutorial that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

Thank you

Warm Regards


Hi BoonBengT_Intel,

I solved the problem myself. Depending on the booting concept it is necessary to adapt the BSP settings in the Software Project.

Thank you for your time!

Best Regards,